linux-imx

// SPDX-License-Identifier: GPL-2.0-only

/*

 * Copyright (C) 2004-2005 Advanced Micro Devices, Inc.

 * Copyright (C)      2007 Bartlomiej Zolnierkiewicz

 *

 * History:

 * 09/20/2005 - Jaya Kumar <jayakumar.ide@gmail.com>

 * - Reworked tuneproc, set_drive, misc mods to prep for mainline

 * - Work was sponsored by CIS (M) Sdn Bhd.

 * Ported to Kernel 2.6.11 on June 26, 2005 by

 *   Wolfgang Zuleger <wolfgang.zuleger@gmx.de>

 *   Alexander Kiausch <alex.kiausch@t-online.de>

 * Originally developed by AMD for 2.4/2.6

 *

 * Development of this chipset driver was funded

 * by the nice folks at National Semiconductor/AMD.

 *

 * Documentation:

 *  CS5535 documentation available from AMD

 */

​

#include <linux/module.h>

#include <linux/pci.h>

#include <linux/ide.h>

​

#define DRV_NAME "cs5535"

​

#define MSR_ATAC_BASE       0x51300000

#define ATAC_GLD_MSR_CAP    (MSR_ATAC_BASE+0)

#define ATAC_GLD_MSR_CONFIG (MSR_ATAC_BASE+0x01)

#define ATAC_GLD_MSR_SMI    (MSR_ATAC_BASE+0x02)

#define ATAC_GLD_MSR_ERROR  (MSR_ATAC_BASE+0x03)

#define ATAC_GLD_MSR_PM     (MSR_ATAC_BASE+0x04)

#define ATAC_GLD_MSR_DIAG   (MSR_ATAC_BASE+0x05)

#define ATAC_IO_BAR     (MSR_ATAC_BASE+0x08)

#define ATAC_RESET      (MSR_ATAC_BASE+0x10)

#define ATAC_CH0D0_PIO      (MSR_ATAC_BASE+0x20)

#define ATAC_CH0D0_DMA      (MSR_ATAC_BASE+0x21)

#define ATAC_CH0D1_PIO      (MSR_ATAC_BASE+0x22)

#define ATAC_CH0D1_DMA      (MSR_ATAC_BASE+0x23)

#define ATAC_PCI_ABRTERR    (MSR_ATAC_BASE+0x24)

#define ATAC_BM0_CMD_PRIM   0x00

#define ATAC_BM0_STS_PRIM   0x02

#define ATAC_BM0_PRD        0x04

#define CS5535_CABLE_DETECT 0x48

​

/* Format I PIO settings. We separate out cmd and data for safer timings */

​

static unsigned int cs5535_pio_cmd_timings[5] =

{ 0xF7F4, 0x53F3, 0x13F1, 0x5131, 0x1131 };

static unsigned int cs5535_pio_dta_timings[5] =

{ 0xF7F4, 0xF173, 0x8141, 0x5131, 0x1131 };

​

static unsigned int cs5535_mwdma_timings[3] =

{ 0x7F0FFFF3, 0x7F035352, 0x7f024241 };

​

static unsigned int cs5535_udma_timings[5] =

{ 0x7F7436A1, 0x7F733481, 0x7F723261, 0x7F713161, 0x7F703061 };

​

/* Macros to check if the register is the reset value -  reset value is an

   invalid timing and indicates the register has not been set previously */

​

#define CS5535_BAD_PIO(timings) ( (timings&~0x80000000UL) == 0x00009172 )

#define CS5535_BAD_DMA(timings) ( (timings & 0x000FFFFF) == 0x00077771 )

​

/****

 *  cs5535_set_speed         -     Configure the chipset to the new speed

 *  @drive: Drive to set up

 *  @speed: desired speed

 *

 *  cs5535_set_speed() configures the chipset to a new speed.

 */

static void cs5535_set_speed(ide_drive_t *drive, const u8 speed)

{

    u32 reg = 0, dummy;

    u8 unit = drive->dn & 1;

​

    /* Set the PIO timings */

    if (speed < XFER_SW_DMA_0) {

        ide_drive_t *pair = ide_get_pair_dev(drive);

        u8 cmd, pioa;

​

        cmd = pioa = speed - XFER_PIO_0;

​

        if (pair) {

            u8 piob = pair->pio_mode - XFER_PIO_0;

​

            if (piob < cmd)

                cmd = piob;

        }

​

        /* Write the speed of the current drive */