linux-imx

/*

 * Copyright (c) 2003-2006 Silicon Graphics, Inc.  All Rights Reserved.

 * Copyright (C) 2008-2009 MontaVista Software, Inc.

 *

 * This program is free software; you can redistribute it and/or modify it

 * under the terms of version 2 of the GNU General Public License

 * as published by the Free Software Foundation.

 *

 * This program is distributed in the hope that it would be useful, but

 * WITHOUT ANY WARRANTY; without even the implied warranty of

 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.

 *

 * You should have received a copy of the GNU General Public

 * License along with this program; if not, write the Free Software

 * Foundation, Inc., 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.

 *

 * For further information regarding this notice, see:

 *

 * http://oss.sgi.com/projects/GenInfo/NoticeExplan

 */

​

#include <linux/module.h>

#include <linux/types.h>

#include <linux/pci.h>

#include <linux/delay.h>

#include <linux/init.h>

#include <linux/kernel.h>

#include <linux/ioport.h>

#include <linux/blkdev.h>

#include <linux/scatterlist.h>

#include <linux/ioc4.h>

#include <linux/io.h>

#include <linux/ide.h>

​

#define DRV_NAME "SGIIOC4"

​

/* IOC4 Specific Definitions */

#define IOC4_CMD_OFFSET     0x100

#define IOC4_CTRL_OFFSET    0x120

#define IOC4_DMA_OFFSET     0x140

#define IOC4_INTR_OFFSET    0x0

​

#define IOC4_TIMING     0x00

#define IOC4_DMA_PTR_L      0x01

#define IOC4_DMA_PTR_H      0x02

#define IOC4_DMA_ADDR_L     0x03

#define IOC4_DMA_ADDR_H     0x04

#define IOC4_BC_DEV     0x05

#define IOC4_BC_MEM     0x06

#define IOC4_DMA_CTRL       0x07

#define IOC4_DMA_END_ADDR   0x08

​

/* Bits in the IOC4 Control/Status Register */

#define IOC4_S_DMA_START    0x01

#define IOC4_S_DMA_STOP     0x02

#define IOC4_S_DMA_DIR      0x04

#define IOC4_S_DMA_ACTIVE   0x08

#define IOC4_S_DMA_ERROR    0x10

#define IOC4_ATA_MEMERR     0x02

​

/* Read/Write Directions */

#define IOC4_DMA_WRITE      0x04

#define IOC4_DMA_READ       0x00

​

/* Interrupt Register Offsets */

#define IOC4_INTR_REG       0x03

#define IOC4_INTR_SET       0x05

#define IOC4_INTR_CLEAR     0x07

​

#define IOC4_IDE_CACHELINE_SIZE 128

#define IOC4_CMD_CTL_BLK_SIZE   0x20

#define IOC4_SUPPORTED_FIRMWARE_REV 46

​

struct ioc4_dma_regs {

    u32 timing_reg0;

    u32 timing_reg1;

    u32 low_mem_ptr;

    u32 high_mem_ptr;

    u32 low_mem_addr;

    u32 high_mem_addr;

    u32 dev_byte_count;

    u32 mem_byte_count;

    u32 status;

};

​

/* Each Physical Region Descriptor Entry size is 16 bytes (2 * 64 bits) */

/* IOC4 has only 1 IDE channel */

#define IOC4_PRD_BYTES      16

#define IOC4_PRD_ENTRIES    (PAGE_SIZE / (4 * IOC4_PRD_BYTES))

​

​

static void sgiioc4_init_hwif_ports(struct ide_hw *hw,