linux-imx

// SPDX-License-Identifier: GPL-2.0

/*

 * mma8452.c - Support for following Freescale / NXP 3-axis accelerometers:

 *

 * device name  digital output  7-bit I2C slave address (pin selectable)

 * ---------------------------------------------------------------------

 * MMA8451Q 14 bit      0x1c / 0x1d

 * MMA8452Q 12 bit      0x1c / 0x1d

 * MMA8453Q 10 bit      0x1c / 0x1d

 * MMA8652FC    12 bit      0x1d

 * MMA8653FC    10 bit      0x1d

 * FXLS8471Q    14 bit      0x1e / 0x1d / 0x1c / 0x1f

 *

 * Copyright 2015 Martin Kepplinger <martink@posteo.de>

 * Copyright 2014 Peter Meerwald <pmeerw@pmeerw.net>

 *

 *

 * TODO: orientation events

 */

​

#include <linux/module.h>

#include <linux/i2c.h>

#include <linux/iio/iio.h>

#include <linux/iio/sysfs.h>

#include <linux/iio/buffer.h>

#include <linux/iio/trigger.h>

#include <linux/iio/trigger_consumer.h>

#include <linux/iio/triggered_buffer.h>

#include <linux/iio/events.h>

#include <linux/delay.h>

#include <linux/of_device.h>

#include <linux/of_irq.h>

#include <linux/pm_runtime.h>

#include <linux/regulator/consumer.h>

​

#define MMA8452_STATUS              0x00

#define  MMA8452_STATUS_DRDY            (BIT(2) | BIT(1) | BIT(0))

#define MMA8452_OUT_X               0x01 /* MSB first */

#define MMA8452_OUT_Y               0x03

#define MMA8452_OUT_Z               0x05

#define MMA8452_INT_SRC             0x0c

#define MMA8452_WHO_AM_I            0x0d

#define MMA8452_DATA_CFG            0x0e

#define  MMA8452_DATA_CFG_FS_MASK       GENMASK(1, 0)

#define  MMA8452_DATA_CFG_FS_2G         0

#define  MMA8452_DATA_CFG_FS_4G         1

#define  MMA8452_DATA_CFG_FS_8G         2

#define  MMA8452_DATA_CFG_HPF_MASK      BIT(4)

#define MMA8452_HP_FILTER_CUTOFF        0x0f

#define  MMA8452_HP_FILTER_CUTOFF_SEL_MASK  GENMASK(1, 0)

#define MMA8452_FF_MT_CFG           0x15

#define  MMA8452_FF_MT_CFG_OAE          BIT(6)

#define  MMA8452_FF_MT_CFG_ELE          BIT(7)

#define MMA8452_FF_MT_SRC           0x16

#define  MMA8452_FF_MT_SRC_XHE          BIT(1)

#define  MMA8452_FF_MT_SRC_YHE          BIT(3)

#define  MMA8452_FF_MT_SRC_ZHE          BIT(5)

#define MMA8452_FF_MT_THS           0x17

#define  MMA8452_FF_MT_THS_MASK         0x7f

#define MMA8452_FF_MT_COUNT         0x18

#define MMA8452_FF_MT_CHAN_SHIFT    3

#define MMA8452_TRANSIENT_CFG           0x1d

#define  MMA8452_TRANSIENT_CFG_CHAN(chan)   BIT(chan + 1)

#define  MMA8452_TRANSIENT_CFG_HPF_BYP      BIT(0)

#define  MMA8452_TRANSIENT_CFG_ELE      BIT(4)

#define MMA8452_TRANSIENT_SRC           0x1e

#define  MMA8452_TRANSIENT_SRC_XTRANSE      BIT(1)

#define  MMA8452_TRANSIENT_SRC_YTRANSE      BIT(3)

#define  MMA8452_TRANSIENT_SRC_ZTRANSE      BIT(5)

#define MMA8452_TRANSIENT_THS           0x1f

#define  MMA8452_TRANSIENT_THS_MASK     GENMASK(6, 0)

#define MMA8452_TRANSIENT_COUNT         0x20

#define MMA8452_TRANSIENT_CHAN_SHIFT 1

#define MMA8452_CTRL_REG1           0x2a

#define  MMA8452_CTRL_ACTIVE            BIT(0)

#define  MMA8452_CTRL_DR_MASK           GENMASK(5, 3)

#define  MMA8452_CTRL_DR_SHIFT          3

#define  MMA8452_CTRL_DR_DEFAULT        0x4 /* 50 Hz sample frequency */

#define MMA8452_CTRL_REG2           0x2b

#define  MMA8452_CTRL_REG2_RST          BIT(6)

#define  MMA8452_CTRL_REG2_MODS_SHIFT       3

#define  MMA8452_CTRL_REG2_MODS_MASK        0x1b

#define MMA8452_CTRL_REG4           0x2d

#define MMA8452_CTRL_REG5           0x2e

#define MMA8452_OFF_X               0x2f

#define MMA8452_OFF_Y               0x30

#define MMA8452_OFF_Z               0x31

​

#define MMA8452_MAX_REG             0x31

​

#define  MMA8452_INT_DRDY           BIT(0)

#define  MMA8452_INT_FF_MT          BIT(2)