linux-imx

/*

 * Synaptics NavPoint (PXA27x SSP/SPI) driver.

 *

 * Copyright (C) 2012 Paul Parsons <lost.distance@yahoo.com>

 *

 * This program is free software; you can redistribute it and/or modify

 * it under the terms of the GNU General Public License version 2 as

 * published by the Free Software Foundation.

 */

​

#include <linux/kernel.h>

#include <linux/module.h>

#include <linux/platform_device.h>

#include <linux/clk.h>

#include <linux/delay.h>

#include <linux/gpio.h>

#include <linux/input.h>

#include <linux/input/navpoint.h>

#include <linux/interrupt.h>

#include <linux/mutex.h>

#include <linux/pxa2xx_ssp.h>

#include <linux/slab.h>

​

/*

 * Synaptics Modular Embedded Protocol: Module Packet Format.

 * Module header byte 2:0 = Length (# bytes that follow)

 * Module header byte 4:3 = Control

 * Module header byte 7:5 = Module Address

 */

#define HEADER_LENGTH(byte) ((byte) & 0x07)

#define HEADER_CONTROL(byte)    (((byte) >> 3) & 0x03)

#define HEADER_ADDRESS(byte)    ((byte) >> 5)

​

struct navpoint {

    struct ssp_device   *ssp;

    struct input_dev    *input;

    struct device       *dev;

    int         gpio;

    int         index;

    u8          data[1 + HEADER_LENGTH(0xff)];

};

​

/*

 * Initialization values for SSCR0_x, SSCR1_x, SSSR_x.

 */

static const u32 sscr0 = 0

    | SSCR0_TUM     /* TIM = 1; No TUR interrupts */

    | SSCR0_RIM     /* RIM = 1; No ROR interrupts */

    | SSCR0_SSE     /* SSE = 1; SSP enabled */

    | SSCR0_Motorola    /* FRF = 0; Motorola SPI */

    | SSCR0_DataSize(16)    /* DSS = 15; Data size = 16-bit */

    ;

static const u32 sscr1 = 0

    | SSCR1_SCFR        /* SCFR = 1; SSPSCLK only during transfers */

    | SSCR1_SCLKDIR     /* SCLKDIR = 1; Slave mode */

    | SSCR1_SFRMDIR     /* SFRMDIR = 1; Slave mode */

    | SSCR1_RWOT        /* RWOT = 1; Receive without transmit mode */

    | SSCR1_RxTresh(1)  /* RFT = 0; Receive FIFO threshold = 1 */

    | SSCR1_SPH     /* SPH = 1; SSPSCLK inactive 0.5 + 1 cycles */

    | SSCR1_RIE     /* RIE = 1; Receive FIFO interrupt enabled */

    ;

static const u32 sssr = 0

    | SSSR_BCE      /* BCE = 1; Clear BCE */