linux-imx

/*

 * IOMMU API for ARM architected SMMU implementations.

 *

 * This program is free software; you can redistribute it and/or modify

 * it under the terms of the GNU General Public License version 2 as

 * published by the Free Software Foundation.

 *

 * This program is distributed in the hope that it will be useful,

 * but WITHOUT ANY WARRANTY; without even the implied warranty of

 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the

 * GNU General Public License for more details.

 *

 * You should have received a copy of the GNU General Public License

 * along with this program; if not, write to the Free Software

 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.

 *

 * Copyright (C) 2013 ARM Limited

 *

 * Author: Will Deacon <will.deacon@arm.com>

 *

 * This driver currently supports:

 *  - SMMUv1 and v2 implementations

 *  - Stream-matching and stream-indexing

 *  - v7/v8 long-descriptor format

 *  - Non-secure access to the SMMU

 *  - Context fault reporting

 *  - Extended Stream ID (16 bit)

 */

​

#define pr_fmt(fmt) "arm-smmu: " fmt

​

#include <linux/acpi.h>

#include <linux/acpi_iort.h>

#include <linux/atomic.h>

#include <linux/delay.h>

#include <linux/dma-iommu.h>

#include <linux/dma-mapping.h>

#include <linux/err.h>

#include <linux/interrupt.h>

#include <linux/io.h>

#include <linux/io-64-nonatomic-hi-lo.h>

#include <linux/io-pgtable.h>

#include <linux/iommu.h>

#include <linux/iopoll.h>

#include <linux/init.h>

#include <linux/moduleparam.h>

#include <linux/of.h>

#include <linux/of_address.h>

#include <linux/of_device.h>

#include <linux/of_iommu.h>

#include <linux/pci.h>

#include <linux/platform_device.h>

#include <linux/pm_runtime.h>

#include <linux/slab.h>

#include <linux/spinlock.h>

​

#include <linux/amba/bus.h>

#include <linux/fsl/mc.h>

​

#include "arm-smmu-regs.h"

​

#define ARM_MMU500_ACTLR_CPRE       (1 << 1)

​

#define ARM_MMU500_ACR_CACHE_LOCK   (1 << 26)

#define ARM_MMU500_ACR_S2CRB_TLBEN  (1 << 10)

#define ARM_MMU500_ACR_SMTNMB_TLBEN (1 << 8)

​

#define TLB_LOOP_TIMEOUT        1000000 /* 1s! */

#define TLB_SPIN_COUNT          10

​

/* Maximum number of context banks per SMMU */

#define ARM_SMMU_MAX_CBS        128

​

/* SMMU global address space */

#define ARM_SMMU_GR0(smmu)      ((smmu)->base)

#define ARM_SMMU_GR1(smmu)      ((smmu)->base + (1 << (smmu)->pgshift))

​

/*

 * SMMU global address space with conditional offset to access secure

 * aliases of non-secure registers (e.g. nsCR0: 0x400, nsGFSR: 0x448,

 * nsGFSYNR0: 0x450)

 */

#define ARM_SMMU_GR0_NS(smmu)                       \

    ((smmu)->base +                         \

        ((smmu->options & ARM_SMMU_OPT_SECURE_CFG_ACCESS)   \

            ? 0x400 : 0))

​

/*

 * Some 64-bit registers only make sense to write atomically, but in such

 * cases all the data relevant to AArch32 formats lies within the lower word,

 * therefore this actually makes more sense than it might first appear.

 */