linux-imx

/*

 * Copyright (c) 2015-2016 MediaTek Inc.

 * Author: Yong Wu <yong.wu@mediatek.com>

 *

 * This program is free software; you can redistribute it and/or modify

 * it under the terms of the GNU General Public License version 2 as

 * published by the Free Software Foundation.

 *

 * This program is distributed in the hope that it will be useful,

 * but WITHOUT ANY WARRANTY; without even the implied warranty of

 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the

 * GNU General Public License for more details.

 */

#include <linux/memblock.h>

#include <linux/bug.h>

#include <linux/clk.h>

#include <linux/component.h>

#include <linux/device.h>

#include <linux/dma-iommu.h>

#include <linux/err.h>

#include <linux/interrupt.h>

#include <linux/io.h>

#include <linux/iommu.h>

#include <linux/iopoll.h>

#include <linux/list.h>

#include <linux/of_address.h>

#include <linux/of_iommu.h>

#include <linux/of_irq.h>

#include <linux/of_platform.h>

#include <linux/platform_device.h>

#include <linux/slab.h>

#include <linux/spinlock.h>

#include <asm/barrier.h>

#include <soc/mediatek/smi.h>

​

#include "mtk_iommu.h"

​

#define REG_MMU_PT_BASE_ADDR            0x000

​

#define REG_MMU_INVALIDATE          0x020

#define F_ALL_INVLD             0x2

#define F_MMU_INV_RANGE             0x1

​

#define REG_MMU_INVLD_START_A           0x024

#define REG_MMU_INVLD_END_A         0x028

​

#define REG_MMU_INV_SEL             0x038

#define F_INVLD_EN0             BIT(0)

#define F_INVLD_EN1             BIT(1)

​

#define REG_MMU_STANDARD_AXI_MODE       0x048

#define REG_MMU_DCM_DIS             0x050

​

#define REG_MMU_CTRL_REG            0x110

#define F_MMU_PREFETCH_RT_REPLACE_MOD       BIT(4)

#define F_MMU_TF_PROTECT_SEL_SHIFT(data) \

    ((data)->m4u_plat == M4U_MT2712 ? 4 : 5)

/* It's named by F_MMU_TF_PROT_SEL in mt2712. */

#define F_MMU_TF_PROTECT_SEL(prot, data) \

    (((prot) & 0x3) << F_MMU_TF_PROTECT_SEL_SHIFT(data))

​

#define REG_MMU_IVRP_PADDR          0x114

​

#define REG_MMU_VLD_PA_RNG          0x118

#define F_MMU_VLD_PA_RNG(EA, SA)        (((EA) << 8) | (SA))

​

#define REG_MMU_INT_CONTROL0            0x120

#define F_L2_MULIT_HIT_EN           BIT(0)

#define F_TABLE_WALK_FAULT_INT_EN       BIT(1)

#define F_PREETCH_FIFO_OVERFLOW_INT_EN      BIT(2)

#define F_MISS_FIFO_OVERFLOW_INT_EN     BIT(3)

#define F_PREFETCH_FIFO_ERR_INT_EN      BIT(5)

#define F_MISS_FIFO_ERR_INT_EN          BIT(6)

#define F_INT_CLR_BIT               BIT(12)

​

#define REG_MMU_INT_MAIN_CONTROL        0x124

#define F_INT_TRANSLATION_FAULT         BIT(0)

#define F_INT_MAIN_MULTI_HIT_FAULT      BIT(1)

#define F_INT_INVALID_PA_FAULT          BIT(2)

#define F_INT_ENTRY_REPLACEMENT_FAULT       BIT(3)

#define F_INT_TLB_MISS_FAULT            BIT(4)

#define F_INT_MISS_TRANSACTION_FIFO_FAULT   BIT(5)

#define F_INT_PRETETCH_TRANSATION_FIFO_FAULT    BIT(6)

​

#define REG_MMU_CPE_DONE            0x12C

​

#define REG_MMU_FAULT_ST1           0x134

​

#define REG_MMU_FAULT_VA            0x13c

#define F_MMU_FAULT_VA_WRITE_BIT        BIT(1)

#define F_MMU_FAULT_VA_LAYER_BIT        BIT(0)

​