linux-imx

/*

 * IOMMU API for Graphics Address Relocation Table on Tegra20

 *

 * Copyright (c) 2010-2012, NVIDIA CORPORATION.  All rights reserved.

 *

 * Author: Hiroshi DOYU <hdoyu@nvidia.com>

 *

 * This program is free software; you can redistribute it and/or modify it

 * under the terms and conditions of the GNU General Public License,

 * version 2, as published by the Free Software Foundation.

 *

 * This program is distributed in the hope it will be useful, but WITHOUT

 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or

 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for

 * more details.

 *

 * You should have received a copy of the GNU General Public License along with

 * this program; if not, write to the Free Software Foundation, Inc.,

 * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.

 */

​

#define dev_fmt(fmt)    "gart: " fmt

​

#include <linux/io.h>

#include <linux/iommu.h>

#include <linux/moduleparam.h>

#include <linux/platform_device.h>

#include <linux/slab.h>

#include <linux/spinlock.h>

#include <linux/vmalloc.h>

​

#include <soc/tegra/mc.h>

​

#define GART_REG_BASE       0x24

#define GART_CONFIG     (0x24 - GART_REG_BASE)

#define GART_ENTRY_ADDR     (0x28 - GART_REG_BASE)

#define GART_ENTRY_DATA     (0x2c - GART_REG_BASE)

​

#define GART_ENTRY_PHYS_ADDR_VALID  BIT(31)

​

#define GART_PAGE_SHIFT     12

#define GART_PAGE_SIZE      (1 << GART_PAGE_SHIFT)

#define GART_PAGE_MASK      GENMASK(30, GART_PAGE_SHIFT)

​

/* bitmap of the page sizes currently supported */

#define GART_IOMMU_PGSIZES  (GART_PAGE_SIZE)

​

struct gart_device {

    void __iomem        *regs;

    u32         *savedata;

    unsigned long       iovmm_base; /* offset to vmm_area start */

    unsigned long       iovmm_end;  /* offset to vmm_area end */

    spinlock_t      pte_lock;   /* for pagetable */

    spinlock_t      dom_lock;   /* for active domain */

    unsigned int        active_devices; /* number of active devices */

    struct iommu_domain *active_domain; /* current active domain */

    struct iommu_device iommu;      /* IOMMU Core handle */

    struct device       *dev;

};

​

static struct gart_device *gart_handle; /* unique for a system */

​

static bool gart_debug;

​

/*

 * Any interaction between any block on PPSB and a block on APB or AHB

 * must have these read-back to ensure the APB/AHB bus transaction is

 * complete before initiating activity on the PPSB block.

 */

#define FLUSH_GART_REGS(gart)   readl_relaxed((gart)->regs + GART_CONFIG)

​

#define for_each_gart_pte(gart, iova)                   \

    for (iova = gart->iovmm_base;                   \

         iova < gart->iovmm_end;                    \

         iova += GART_PAGE_SIZE)

​

static inline void gart_set_pte(struct gart_device *gart,

                unsigned long iova, unsigned long pte)

{

    writel_relaxed(iova, gart->regs + GART_ENTRY_ADDR);

    writel_relaxed(pte, gart->regs + GART_ENTRY_DATA);

}

​

static inline unsigned long gart_read_pte(struct gart_device *gart,

                      unsigned long iova)

{

    unsigned long pte;

​

    writel_relaxed(iova, gart->regs + GART_ENTRY_ADDR);

    pte = readl_relaxed(gart->regs + GART_ENTRY_DATA);

​

    return pte;