linux-imx

/*

 * Generic Broadcom Set Top Box Level 2 Interrupt controller driver

 *

 * Copyright (C) 2014-2017 Broadcom

 *

 * This program is free software; you can redistribute it and/or modify

 * it under the terms of the GNU General Public License version 2 as

 * published by the Free Software Foundation.

 *

 * This program is distributed in the hope that it will be useful,

 * but WITHOUT ANY WARRANTY; without even the implied warranty of

 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the

 * GNU General Public License for more details.

 */

​

#define pr_fmt(fmt) KBUILD_MODNAME  ": " fmt

​

#include <linux/init.h>

#include <linux/slab.h>

#include <linux/module.h>

#include <linux/platform_device.h>

#include <linux/spinlock.h>

#include <linux/of.h>

#include <linux/of_irq.h>

#include <linux/of_address.h>

#include <linux/of_platform.h>

#include <linux/interrupt.h>

#include <linux/irq.h>

#include <linux/io.h>

#include <linux/irqdomain.h>

#include <linux/irqchip.h>

#include <linux/irqchip/chained_irq.h>

​

struct brcmstb_intc_init_params {

    irq_flow_handler_t handler;

    int cpu_status;

    int cpu_clear;

    int cpu_mask_status;

    int cpu_mask_set;

    int cpu_mask_clear;

};

​

/* Register offsets in the L2 latched interrupt controller */

static const struct brcmstb_intc_init_params l2_edge_intc_init = {

    .handler        = handle_edge_irq,

    .cpu_status     = 0x00,

    .cpu_clear      = 0x08,

    .cpu_mask_status    = 0x0c,

    .cpu_mask_set       = 0x10,

    .cpu_mask_clear     = 0x14

};

​

/* Register offsets in the L2 level interrupt controller */

static const struct brcmstb_intc_init_params l2_lvl_intc_init = {

    .handler        = handle_level_irq,

    .cpu_status     = 0x00,

    .cpu_clear      = -1, /* Register not present */

    .cpu_mask_status    = 0x04,

    .cpu_mask_set       = 0x08,

    .cpu_mask_clear     = 0x0C

};

​

/* L2 intc private data structure */

struct brcmstb_l2_intc_data {

    struct irq_domain *domain;

    struct irq_chip_generic *gc;

    int status_offset;

    int mask_offset;

    bool can_wake;

    u32 saved_mask; /* for suspend/resume */

};

​

/**

 * brcmstb_l2_mask_and_ack - Mask and ack pending interrupt

 * @d: irq_data

 *

 * Chip has separate enable/disable registers instead of a single mask

 * register and pending interrupt is acknowledged by setting a bit.

 *

 * Note: This function is generic and could easily be added to the

 * generic irqchip implementation if there ever becomes a will to do so.

 * Perhaps with a name like irq_gc_mask_disable_and_ack_set().

 *

 * e.g.: https://patchwork.kernel.org/patch/9831047/

 */

static void brcmstb_l2_mask_and_ack(struct irq_data *d)

{

    struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);

    struct irq_chip_type *ct = irq_data_get_chip_type(d);

    u32 mask = d->mask;

​

    irq_gc_lock(gc);