#include <linux/kernel.h>
#include <linux/interrupt.h>
#include <linux/irqchip/irq-davinci-aintc.h>
#include <linux/irqdomain.h>
#include <asm/exception.h>
#define DAVINCI_AINTC_FIQ_REG0 0x00
#define DAVINCI_AINTC_FIQ_REG1 0x04
#define DAVINCI_AINTC_IRQ_REG0 0x08
#define DAVINCI_AINTC_IRQ_REG1 0x0c
#define DAVINCI_AINTC_IRQ_IRQENTRY 0x14
#define DAVINCI_AINTC_IRQ_ENT_REG0 0x18
#define DAVINCI_AINTC_IRQ_ENT_REG1 0x1c
#define DAVINCI_AINTC_IRQ_INCTL_REG 0x20
#define DAVINCI_AINTC_IRQ_EABASE_REG 0x24
#define DAVINCI_AINTC_IRQ_INTPRI0_REG 0x30
#define DAVINCI_AINTC_IRQ_INTPRI7_REG 0x4c
static void __iomem *davinci_aintc_base;
static struct irq_domain *davinci_aintc_irq_domain;
static inline void davinci_aintc_writel(unsigned long value, int offset)
writel_relaxed(value, davinci_aintc_base + offset);
static inline unsigned long davinci_aintc_readl(int offset)
return readl_relaxed(davinci_aintc_base + offset);
davinci_aintc_setup_gc(void __iomem *base,
unsigned int irq_start, unsigned int num)
struct irq_chip_generic *gc;
struct irq_chip_type *ct;
gc = irq_get_domain_generic_chip(davinci_aintc_irq_domain, irq_start);
gc->irq_base = irq_start;
ct->chip.irq_ack = irq_gc_ack_set_bit;
ct->chip.irq_mask = irq_gc_mask_clr_bit;
ct->chip.irq_unmask = irq_gc_mask_set_bit;
ct->regs.ack = DAVINCI_AINTC_IRQ_REG0;
ct->regs.mask = DAVINCI_AINTC_IRQ_ENT_REG0;
irq_setup_generic_chip(gc, IRQ_MSK(num), IRQ_GC_INIT_MASK_CACHE,
IRQ_NOREQUEST | IRQ_NOPROBE, 0);