linux-imx

/*

 * Copyright (c) 2016, Mellanox Technologies. All rights reserved.

 *

 * This software is available to you under a choice of one of two

 * licenses.  You may choose to be licensed under the terms of the GNU

 * General Public License (GPL) Version 2, available from the file

 * COPYING in the main directory of this source tree, or the

 * OpenIB.org BSD license below:

 *

 *     Redistribution and use in source and binary forms, with or

 *     without modification, are permitted provided that the following

 *     conditions are met:

 *

 *      - Redistributions of source code must retain the above

 *        copyright notice, this list of conditions and the following

 *        disclaimer.

 *

 *      - Redistributions in binary form must reproduce the above

 *        copyright notice, this list of conditions and the following

 *        disclaimer in the documentation and/or other materials

 *        provided with the distribution.

 *

 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,

 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF

 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND

 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS

 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN

 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN

 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE

 * SOFTWARE.

 */

​

#include <linux/interrupt.h>

#include <linux/module.h>

#include <linux/of.h>

#include <linux/irq.h>

#include <linux/irqdomain.h>

#include <linux/irqchip.h>

#include <soc/nps/common.h>

​

#define NPS_NR_CPU_IRQS 8  /* number of interrupt lines of NPS400 CPU */

#define NPS_TIMER0_IRQ  3

​

/*

 * NPS400 core includes an Interrupt Controller (IC) support.

 * All cores can deactivate level irqs at first level control

 * at cores mesh layer called MTM.

 * For devices out side chip e.g. uart, network there is another

 * level called Global Interrupt Manager (GIM).

 * This second level can control level and edge interrupt.

 *

 * NOTE: AUX_IENABLE and CTOP_AUX_IACK are auxiliary registers

 * with private HW copy per CPU.

 */

​

static void nps400_irq_mask(struct irq_data *irqd)

{

    unsigned int ienb;

    unsigned int irq = irqd_to_hwirq(irqd);

​

    ienb = read_aux_reg(AUX_IENABLE);

    ienb &= ~(1 << irq);

    write_aux_reg(AUX_IENABLE, ienb);