linux-imx

/*

 * ARM GIC v2m MSI(-X) support

 * Support for Message Signaled Interrupts for systems that

 * implement ARM Generic Interrupt Controller: GICv2m.

 *

 * Copyright (C) 2014 Advanced Micro Devices, Inc.

 * Authors: Suravee Suthikulpanit <suravee.suthikulpanit@amd.com>

 *      Harish Kasiviswanathan <harish.kasiviswanathan@amd.com>

 *      Brandon Anderson <brandon.anderson@amd.com>

 *

 * This program is free software; you can redistribute it and/or modify it

 * under the terms of the GNU General Public License version 2 as published

 * by the Free Software Foundation.

 */

​

#define pr_fmt(fmt) "GICv2m: " fmt

​

#include <linux/acpi.h>

#include <linux/dma-iommu.h>

#include <linux/irq.h>

#include <linux/irqdomain.h>

#include <linux/kernel.h>

#include <linux/msi.h>

#include <linux/of_address.h>

#include <linux/of_pci.h>

#include <linux/slab.h>

#include <linux/spinlock.h>

#include <linux/irqchip/arm-gic.h>

​

/*

* MSI_TYPER:

*     [31:26] Reserved

*     [25:16] lowest SPI assigned to MSI

*     [15:10] Reserved

*     [9:0]   Numer of SPIs assigned to MSI

*/

#define V2M_MSI_TYPER              0x008

#define V2M_MSI_TYPER_BASE_SHIFT       16

#define V2M_MSI_TYPER_BASE_MASK        0x3FF

#define V2M_MSI_TYPER_NUM_MASK         0x3FF

#define V2M_MSI_SETSPI_NS          0x040

#define V2M_MIN_SPI            32

#define V2M_MAX_SPI            1019

#define V2M_MSI_IIDR               0xFCC

​

#define V2M_MSI_TYPER_BASE_SPI(x)      \

           (((x) >> V2M_MSI_TYPER_BASE_SHIFT) & V2M_MSI_TYPER_BASE_MASK)

​

#define V2M_MSI_TYPER_NUM_SPI(x)       ((x) & V2M_MSI_TYPER_NUM_MASK)

​

/* APM X-Gene with GICv2m MSI_IIDR register value */

#define XGENE_GICV2M_MSI_IIDR       0x06000170

​

/* Broadcom NS2 GICv2m MSI_IIDR register value */

#define BCM_NS2_GICV2M_MSI_IIDR     0x0000013f

​

/* List of flags for specific v2m implementation */

#define GICV2M_NEEDS_SPI_OFFSET     0x00000001

​

static LIST_HEAD(v2m_nodes);

static DEFINE_SPINLOCK(v2m_lock);

​

struct v2m_data {

    struct list_head entry;

    struct fwnode_handle *fwnode;

    struct resource res;    /* GICv2m resource */

    void __iomem *base; /* GICv2m virt address */

    u32 spi_start;      /* The SPI number that MSIs start */

    u32 nr_spis;        /* The number of SPIs for MSIs */

    u32 spi_offset;     /* offset to be subtracted from SPI number */

    unsigned long *bm;  /* MSI vector bitmap */

    u32 flags;      /* v2m flags for specific implementation */

};

​

static void gicv2m_mask_msi_irq(struct irq_data *d)

{

    pci_msi_mask_irq(d);

    irq_chip_mask_parent(d);

}

​

static void gicv2m_unmask_msi_irq(struct irq_data *d)

{

    pci_msi_unmask_irq(d);

    irq_chip_unmask_parent(d);

}

​

static struct irq_chip gicv2m_msi_irq_chip = {

    .name           = "MSI",

    .irq_mask       = gicv2m_mask_msi_irq,

    .irq_unmask     = gicv2m_unmask_msi_irq,

    .irq_eoi        = irq_chip_eoi_parent,

    .irq_write_msi_msg  = pci_msi_domain_write_msg,