linux-imx

/*

 * Copyright (C) 2013-2017 ARM Limited, All Rights Reserved.

 * Author: Marc Zyngier <marc.zyngier@arm.com>

 *

 * This program is free software; you can redistribute it and/or modify

 * it under the terms of the GNU General Public License version 2 as

 * published by the Free Software Foundation.

 *

 * This program is distributed in the hope that it will be useful,

 * but WITHOUT ANY WARRANTY; without even the implied warranty of

 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the

 * GNU General Public License for more details.

 *

 * You should have received a copy of the GNU General Public License

 * along with this program.  If not, see <http://www.gnu.org/licenses/>.

 */

​

#include <linux/acpi.h>

#include <linux/acpi_iort.h>

#include <linux/bitmap.h>

#include <linux/cpu.h>

#include <linux/crash_dump.h>

#include <linux/delay.h>

#include <linux/dma-iommu.h>

#include <linux/efi.h>

#include <linux/interrupt.h>

#include <linux/irqdomain.h>

#include <linux/list.h>

#include <linux/list_sort.h>

#include <linux/log2.h>

#include <linux/memblock.h>

#include <linux/mm.h>

#include <linux/msi.h>

#include <linux/of.h>

#include <linux/of_address.h>

#include <linux/of_irq.h>

#include <linux/of_pci.h>

#include <linux/of_platform.h>

#include <linux/percpu.h>

#include <linux/slab.h>

#include <linux/syscore_ops.h>

​

#include <linux/irqchip.h>

#include <linux/irqchip/arm-gic-v3.h>

#include <linux/irqchip/arm-gic-v4.h>

​

#include <asm/cputype.h>

#include <asm/exception.h>

​

#include "irq-gic-common.h"

​

#define ITS_FLAGS_CMDQ_NEEDS_FLUSHING       (1ULL << 0)

#define ITS_FLAGS_WORKAROUND_CAVIUM_22375   (1ULL << 1)

#define ITS_FLAGS_WORKAROUND_CAVIUM_23144   (1ULL << 2)

#define ITS_FLAGS_SAVE_SUSPEND_STATE        (1ULL << 3)

​

#define RDIST_FLAGS_PROPBASE_NEEDS_FLUSHING (1 << 0)

#define RDIST_FLAGS_RD_TABLES_PREALLOCATED  (1 << 1)

​

static u32 lpi_id_bits;

​

/*

 * We allocate memory for PROPBASE to cover 2 ^ lpi_id_bits LPIs to

 * deal with (one configuration byte per interrupt). PENDBASE has to

 * be 64kB aligned (one bit per LPI, plus 8192 bits for SPI/PPI/SGI).

 */

#define LPI_NRBITS      lpi_id_bits

#define LPI_PROPBASE_SZ     ALIGN(BIT(LPI_NRBITS), SZ_64K)

#define LPI_PENDBASE_SZ     ALIGN(BIT(LPI_NRBITS) / 8, SZ_64K)

​

#define LPI_PROP_DEFAULT_PRIO   GICD_INT_DEF_PRI

​

/*

 * Collection structure - just an ID, and a redistributor address to

 * ping. We use one per CPU as a bag of interrupts assigned to this

 * CPU.

 */

struct its_collection {

    u64         target_address;

    u16         col_id;

};

​

/*

 * The ITS_BASER structure - contains memory information, cached

 * value of BASER register configuration and ITS page size.

 */

struct its_baser {

    void        *base;

    u64     val;

    u32     order;

    u32     psz;

};