linux-imx

/*

 * Copyright 2001 MontaVista Software Inc.

 * Author: Jun Sun, jsun@mvista.com or jsun@junsun.net

 *

 * Copyright (C) 2001 Ralf Baechle

 * Copyright (C) 2005  MIPS Technologies, Inc.  All rights reserved.

 *  Author: Maciej W. Rozycki <macro@mips.com>

 *

 * This file define the irq handler for MIPS CPU interrupts.

 *

 * This program is free software; you can redistribute  it and/or modify it

 * under  the terms of  the GNU General  Public License as published by the

 * Free Software Foundation;  either version 2 of the  License, or (at your

 * option) any later version.

 */

​

/*

 * Almost all MIPS CPUs define 8 interrupt sources.  They are typically

 * level triggered (i.e., cannot be cleared from CPU; must be cleared from

 * device).

 *

 * The first two are software interrupts (i.e. not exposed as pins) which

 * may be used for IPIs in multi-threaded single-core systems.

 *

 * The last one is usually the CPU timer interrupt if the counter register

 * is present, or for old CPUs with an external FPU by convention it's the

 * FPU exception interrupt.

 */

#include <linux/init.h>

#include <linux/interrupt.h>

#include <linux/kernel.h>

#include <linux/irq.h>

#include <linux/irqchip.h>

#include <linux/irqdomain.h>

​

#include <asm/irq_cpu.h>

#include <asm/mipsregs.h>

#include <asm/mipsmtregs.h>

#include <asm/setup.h>

​

static struct irq_domain *irq_domain;

static struct irq_domain *ipi_domain;

​

static inline void unmask_mips_irq(struct irq_data *d)

{

    set_c0_status(IE_SW0 << d->hwirq);

    irq_enable_hazard();

}

​

static inline void mask_mips_irq(struct irq_data *d)

{

    clear_c0_status(IE_SW0 << d->hwirq);

    irq_disable_hazard();

}

​

static struct irq_chip mips_cpu_irq_controller = {

    .name       = "MIPS",

    .irq_ack    = mask_mips_irq,

    .irq_mask   = mask_mips_irq,

    .irq_mask_ack   = mask_mips_irq,

    .irq_unmask = unmask_mips_irq,

    .irq_eoi    = unmask_mips_irq,

    .irq_disable    = mask_mips_irq,

    .irq_enable = unmask_mips_irq,

};

​

/*

 * Basically the same as above but taking care of all the MT stuff

 */

​

static unsigned int mips_mt_cpu_irq_startup(struct irq_data *d)

{

    unsigned int vpflags = dvpe();

​

    clear_c0_cause(C_SW0 << d->hwirq);

    evpe(vpflags);

    unmask_mips_irq(d);

    return 0;

}

​

/*

 * While we ack the interrupt interrupts are disabled and thus we don't need

 * to deal with concurrency issues.  Same for mips_cpu_irq_end.

 */

static void mips_mt_cpu_irq_ack(struct irq_data *d)

{

    unsigned int vpflags = dvpe();

    clear_c0_cause(C_SW0 << d->hwirq);

    evpe(vpflags);

    mask_mips_irq(d);

}

​