linux-imx

/*

 * This file is subject to the terms and conditions of the GNU General Public

 * License.  See the file "COPYING" in the main directory of this archive

 * for more details.

 *

 * Copyright (C) 2008 Ralf Baechle (ralf@linux-mips.org)

 * Copyright (C) 2012 MIPS Technologies, Inc.  All rights reserved.

 */

​

#define pr_fmt(fmt) "irq-mips-gic: " fmt

​

#include <linux/bitmap.h>

#include <linux/clocksource.h>

#include <linux/cpuhotplug.h>

#include <linux/init.h>

#include <linux/interrupt.h>

#include <linux/irq.h>

#include <linux/irqchip.h>

#include <linux/of_address.h>

#include <linux/percpu.h>

#include <linux/sched.h>

#include <linux/smp.h>

​

#include <asm/mips-cps.h>

#include <asm/setup.h>

#include <asm/traps.h>

​

#include <dt-bindings/interrupt-controller/mips-gic.h>

​

#define GIC_MAX_INTRS       256

#define GIC_MAX_LONGS       BITS_TO_LONGS(GIC_MAX_INTRS)

​

/* Add 2 to convert GIC CPU pin to core interrupt */

#define GIC_CPU_PIN_OFFSET  2

​

/* Mapped interrupt to pin X, then GIC will generate the vector (X+1). */

#define GIC_PIN_TO_VEC_OFFSET   1

​

/* Convert between local/shared IRQ number and GIC HW IRQ number. */

#define GIC_LOCAL_HWIRQ_BASE    0

#define GIC_LOCAL_TO_HWIRQ(x)   (GIC_LOCAL_HWIRQ_BASE + (x))

#define GIC_HWIRQ_TO_LOCAL(x)   ((x) - GIC_LOCAL_HWIRQ_BASE)

#define GIC_SHARED_HWIRQ_BASE   GIC_NUM_LOCAL_INTRS

#define GIC_SHARED_TO_HWIRQ(x)  (GIC_SHARED_HWIRQ_BASE + (x))

#define GIC_HWIRQ_TO_SHARED(x)  ((x) - GIC_SHARED_HWIRQ_BASE)

​

void __iomem *mips_gic_base;

​

DEFINE_PER_CPU_READ_MOSTLY(unsigned long[GIC_MAX_LONGS], pcpu_masks);

​

static DEFINE_SPINLOCK(gic_lock);

static struct irq_domain *gic_irq_domain;

static struct irq_domain *gic_ipi_domain;

static int gic_shared_intrs;

static unsigned int gic_cpu_pin;

static unsigned int timer_cpu_pin;

static struct irq_chip gic_level_irq_controller, gic_edge_irq_controller;

static DECLARE_BITMAP(ipi_resrv, GIC_MAX_INTRS);

static DECLARE_BITMAP(ipi_available, GIC_MAX_INTRS);

​

static struct gic_all_vpes_chip_data {

    u32 map;

    bool    mask;

} gic_all_vpes_chip_data[GIC_NUM_LOCAL_INTRS];

​

static void gic_clear_pcpu_masks(unsigned int intr)

{

    unsigned int i;

​

    /* Clear the interrupt's bit in all pcpu_masks */

    for_each_possible_cpu(i)

        clear_bit(intr, per_cpu_ptr(pcpu_masks, i));

}

​

static bool gic_local_irq_is_routable(int intr)

{

    u32 vpe_ctl;

​

    /* All local interrupts are routable in EIC mode. */

    if (cpu_has_veic)

        return true;

​

    vpe_ctl = read_gic_vl_ctl();

    switch (intr) {

    case GIC_LOCAL_INT_TIMER:

        return vpe_ctl & GIC_VX_CTL_TIMER_ROUTABLE;

    case GIC_LOCAL_INT_PERFCTR:

        return vpe_ctl & GIC_VX_CTL_PERFCNT_ROUTABLE;

    case GIC_LOCAL_INT_FDC:

        return vpe_ctl & GIC_VX_CTL_FDC_ROUTABLE;

    case GIC_LOCAL_INT_SWINT0:

    case GIC_LOCAL_INT_SWINT1: