linux-imx

/*

 * Copyright (C) 2010-2011 Jonas Bonn <jonas@southpole.se>

 * Copyright (C) 2014 Stefan Kristansson <stefan.kristiansson@saunalahti.fi>

 *

 * This program is free software; you can redistribute it and/or

 * modify it under the terms of the GNU General Public License

 * as published by the Free Software Foundation; either version

 * 2 of the License, or (at your option) any later version.

 */

​

#include <linux/irq.h>

#include <linux/irqchip.h>

#include <linux/of.h>

#include <linux/of_irq.h>

#include <linux/of_address.h>

​

/* OR1K PIC implementation */

​

struct or1k_pic_dev {

    struct irq_chip chip;

    irq_flow_handler_t handle;

    unsigned long flags;

};

​

/*

 * We're a couple of cycles faster than the generic implementations with

 * these 'fast' versions.

 */

​

static void or1k_pic_mask(struct irq_data *data)

{

    mtspr(SPR_PICMR, mfspr(SPR_PICMR) & ~(1UL << data->hwirq));

}

​

static void or1k_pic_unmask(struct irq_data *data)

{

    mtspr(SPR_PICMR, mfspr(SPR_PICMR) | (1UL << data->hwirq));

}

​

static void or1k_pic_ack(struct irq_data *data)

{

    mtspr(SPR_PICSR, (1UL << data->hwirq));

}

​

static void or1k_pic_mask_ack(struct irq_data *data)

{

    mtspr(SPR_PICMR, mfspr(SPR_PICMR) & ~(1UL << data->hwirq));

    mtspr(SPR_PICSR, (1UL << data->hwirq));

}

​

/*

 * There are two oddities with the OR1200 PIC implementation:

 * i)  LEVEL-triggered interrupts are latched and need to be cleared

 * ii) the interrupt latch is cleared by writing a 0 to the bit,

 *     as opposed to a 1 as mandated by the spec

 */

static void or1k_pic_or1200_ack(struct irq_data *data)

{

    mtspr(SPR_PICSR, mfspr(SPR_PICSR) & ~(1UL << data->hwirq));

}

​

static void or1k_pic_or1200_mask_ack(struct irq_data *data)

{