linux-imx

// SPDX-License-Identifier: GPL-2.0

/*

 * Renesas INTC External IRQ Pin Driver

 *

 *  Copyright (C) 2013 Magnus Damm

 */

​

#include <linux/init.h>

#include <linux/of.h>

#include <linux/platform_device.h>

#include <linux/spinlock.h>

#include <linux/interrupt.h>

#include <linux/ioport.h>

#include <linux/io.h>

#include <linux/irq.h>

#include <linux/irqdomain.h>

#include <linux/err.h>

#include <linux/slab.h>

#include <linux/module.h>

#include <linux/of_device.h>

#include <linux/pm_runtime.h>

​

#define INTC_IRQPIN_MAX 8 /* maximum 8 interrupts per driver instance */

​

#define INTC_IRQPIN_REG_SENSE 0 /* ICRn */

#define INTC_IRQPIN_REG_PRIO 1 /* INTPRInn */

#define INTC_IRQPIN_REG_SOURCE 2 /* INTREQnn */

#define INTC_IRQPIN_REG_MASK 3 /* INTMSKnn */

#define INTC_IRQPIN_REG_CLEAR 4 /* INTMSKCLRnn */

#define INTC_IRQPIN_REG_NR_MANDATORY 5

#define INTC_IRQPIN_REG_IRLM 5 /* ICR0 with IRLM bit (optional) */

#define INTC_IRQPIN_REG_NR 6

​

/* INTC external IRQ PIN hardware register access:

 *

 * SENSE is read-write 32-bit with 2-bits or 4-bits per IRQ (*)

 * PRIO is read-write 32-bit with 4-bits per IRQ (**)

 * SOURCE is read-only 32-bit or 8-bit with 1-bit per IRQ (***)

 * MASK is write-only 32-bit or 8-bit with 1-bit per IRQ (***)

 * CLEAR is write-only 32-bit or 8-bit with 1-bit per IRQ (***)

 *

 * (*) May be accessed by more than one driver instance - lock needed

 * (**) Read-modify-write access by one driver instance - lock needed

 * (***) Accessed by one driver instance only - no locking needed

 */

​

struct intc_irqpin_iomem {

    void __iomem *iomem;

    unsigned long (*read)(void __iomem *iomem);

    void (*write)(void __iomem *iomem, unsigned long data);

    int width;

};

​

struct intc_irqpin_irq {

    int hw_irq;

    int requested_irq;

    int domain_irq;

    struct intc_irqpin_priv *p;

};

​

struct intc_irqpin_priv {

    struct intc_irqpin_iomem iomem[INTC_IRQPIN_REG_NR];

    struct intc_irqpin_irq irq[INTC_IRQPIN_MAX];

    unsigned int sense_bitfield_width;

    struct platform_device *pdev;

    struct irq_chip irq_chip;

    struct irq_domain *irq_domain;

    atomic_t wakeup_path;

    unsigned shared_irqs:1;

    u8 shared_irq_mask;

};

​

struct intc_irqpin_config {

    unsigned int irlm_bit;

    unsigned needs_irlm:1;

};

​

static unsigned long intc_irqpin_read32(void __iomem *iomem)

{

    return ioread32(iomem);

}

​

static unsigned long intc_irqpin_read8(void __iomem *iomem)

{

    return ioread8(iomem);

}

​

static void intc_irqpin_write32(void __iomem *iomem, unsigned long data)

{

    iowrite32(data, iomem);

}

​