linux-imx

// SPDX-License-Identifier: GPL-2.0

/*

 * Renesas IRQC Driver

 *

 *  Copyright (C) 2013 Magnus Damm

 */

​

#include <linux/init.h>

#include <linux/platform_device.h>

#include <linux/spinlock.h>

#include <linux/interrupt.h>

#include <linux/ioport.h>

#include <linux/io.h>

#include <linux/irq.h>

#include <linux/irqdomain.h>

#include <linux/err.h>

#include <linux/slab.h>

#include <linux/module.h>

#include <linux/pm_runtime.h>

​

#define IRQC_IRQ_MAX    32  /* maximum 32 interrupts per driver instance */

​

#define IRQC_REQ_STS    0x00    /* Interrupt Request Status Register */

#define IRQC_EN_STS 0x04    /* Interrupt Enable Status Register */

#define IRQC_EN_SET 0x08    /* Interrupt Enable Set Register */

#define IRQC_INT_CPU_BASE(n) (0x000 + ((n) * 0x10))

                /* SYS-CPU vs. RT-CPU */

#define DETECT_STATUS   0x100   /* IRQn Detect Status Register */

#define MONITOR     0x104   /* IRQn Signal Level Monitor Register */

#define HLVL_STS    0x108   /* IRQn High Level Detect Status Register */

#define LLVL_STS    0x10c   /* IRQn Low Level Detect Status Register */

#define S_R_EDGE_STS    0x110   /* IRQn Sync Rising Edge Detect Status Reg. */

#define S_F_EDGE_STS    0x114   /* IRQn Sync Falling Edge Detect Status Reg. */

#define A_R_EDGE_STS    0x118   /* IRQn Async Rising Edge Detect Status Reg. */

#define A_F_EDGE_STS    0x11c   /* IRQn Async Falling Edge Detect Status Reg. */

#define CHTEN_STS   0x120   /* Chattering Reduction Status Register */

#define IRQC_CONFIG(n) (0x180 + ((n) * 0x04))

                /* IRQn Configuration Register */

​

struct irqc_irq {

    int hw_irq;

    int requested_irq;

    struct irqc_priv *p;

};

​

struct irqc_priv {

    void __iomem *iomem;

    void __iomem *cpu_int_base;

    struct irqc_irq irq[IRQC_IRQ_MAX];

    unsigned int number_of_irqs;

    struct platform_device *pdev;

    struct irq_chip_generic *gc;

    struct irq_domain *irq_domain;

    atomic_t wakeup_path;

};

​

static struct irqc_priv *irq_data_to_priv(struct irq_data *data)

{

    return data->domain->host_data;

}

​

static void irqc_dbg(struct irqc_irq *i, char *str)

{

    dev_dbg(&i->p->pdev->dev, "%s (%d:%d)\n",

        str, i->requested_irq, i->hw_irq);

}

​

static unsigned char irqc_sense[IRQ_TYPE_SENSE_MASK + 1] = {

    [IRQ_TYPE_LEVEL_LOW]    = 0x01,

    [IRQ_TYPE_LEVEL_HIGH]   = 0x02,

    [IRQ_TYPE_EDGE_FALLING] = 0x04, /* Synchronous */

    [IRQ_TYPE_EDGE_RISING]  = 0x08, /* Synchronous */

    [IRQ_TYPE_EDGE_BOTH]    = 0x0c, /* Synchronous */

};

​

static int irqc_irq_set_type(struct irq_data *d, unsigned int type)

{

    struct irqc_priv *p = irq_data_to_priv(d);

    int hw_irq = irqd_to_hwirq(d);

    unsigned char value = irqc_sense[type & IRQ_TYPE_SENSE_MASK];

    u32 tmp;

​

    irqc_dbg(&p->irq[hw_irq], "sense");

​

    if (!value)

        return -EINVAL;

​

    tmp = ioread32(p->iomem + IRQC_CONFIG(hw_irq));

    tmp &= ~0x3f;

    tmp |= value;

    iowrite32(tmp, p->iomem + IRQC_CONFIG(hw_irq));

    return 0;