linux-imx

/*

 * Driver code for Tegra's Legacy Interrupt Controller

 *

 * Author: Marc Zyngier <marc.zyngier@arm.com>

 *

 * Heavily based on the original arch/arm/mach-tegra/irq.c code:

 * Copyright (C) 2011 Google, Inc.

 *

 * Author:

 *  Colin Cross <ccross@android.com>

 *

 * Copyright (C) 2010,2013, NVIDIA Corporation

 *

 * This software is licensed under the terms of the GNU General Public

 * License version 2, as published by the Free Software Foundation, and

 * may be copied, distributed, and modified under those terms.

 *

 * This program is distributed in the hope that it will be useful,

 * but WITHOUT ANY WARRANTY; without even the implied warranty of

 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the

 * GNU General Public License for more details.

 *

 */

​

#include <linux/io.h>

#include <linux/irq.h>

#include <linux/irqchip.h>

#include <linux/irqdomain.h>

#include <linux/of_address.h>

#include <linux/slab.h>

#include <linux/syscore_ops.h>

​

#include <dt-bindings/interrupt-controller/arm-gic.h>

​

#define ICTLR_CPU_IEP_VFIQ  0x08

#define ICTLR_CPU_IEP_FIR   0x14

#define ICTLR_CPU_IEP_FIR_SET   0x18

#define ICTLR_CPU_IEP_FIR_CLR   0x1c

​

#define ICTLR_CPU_IER       0x20

#define ICTLR_CPU_IER_SET   0x24

#define ICTLR_CPU_IER_CLR   0x28

#define ICTLR_CPU_IEP_CLASS 0x2C

​

#define ICTLR_COP_IER       0x30

#define ICTLR_COP_IER_SET   0x34

#define ICTLR_COP_IER_CLR   0x38

#define ICTLR_COP_IEP_CLASS 0x3c

​

#define TEGRA_MAX_NUM_ICTLRS    6

​

static unsigned int num_ictlrs;

​

struct tegra_ictlr_soc {

    unsigned int num_ictlrs;

};

​

static const struct tegra_ictlr_soc tegra20_ictlr_soc = {

    .num_ictlrs = 4,

};

​

static const struct tegra_ictlr_soc tegra30_ictlr_soc = {

    .num_ictlrs = 5,