linux-imx

// SPDX-License-Identifier: GPL-2.0

/*

 * Copyright (C) STMicroelectronics 2018 - All Rights Reserved

 * Authors: Ludovic Barre <ludovic.barre@st.com> for STMicroelectronics.

 *          Fabien Dessenne <fabien.dessenne@st.com> for STMicroelectronics.

 */

​

#include <linux/bitfield.h>

#include <linux/clk.h>

#include <linux/interrupt.h>

#include <linux/mailbox_controller.h>

#include <linux/module.h>

#include <linux/of_irq.h>

#include <linux/platform_device.h>

#include <linux/pm_wakeirq.h>

​

#define IPCC_XCR        0x000

#define XCR_RXOIE       BIT(0)

#define XCR_TXOIE       BIT(16)

​

#define IPCC_XMR        0x004

#define IPCC_XSCR       0x008

#define IPCC_XTOYSR     0x00c

​

#define IPCC_PROC_OFFST     0x010

​

#define IPCC_HWCFGR     0x3f0

#define IPCFGR_CHAN_MASK    GENMASK(7, 0)

​

#define IPCC_VER        0x3f4

#define VER_MINREV_MASK     GENMASK(3, 0)

#define VER_MAJREV_MASK     GENMASK(7, 4)

​

#define RX_BIT_MASK     GENMASK(15, 0)

#define RX_BIT_CHAN(chan)   BIT(chan)

#define TX_BIT_SHIFT        16

#define TX_BIT_MASK     GENMASK(31, 16)

#define TX_BIT_CHAN(chan)   BIT(TX_BIT_SHIFT + (chan))

​

#define STM32_MAX_PROCS     2

​

enum {

    IPCC_IRQ_RX,

    IPCC_IRQ_TX,

    IPCC_IRQ_NUM,

};

​

struct stm32_ipcc {

    struct mbox_controller controller;

    void __iomem *reg_base;

    void __iomem *reg_proc;

    struct clk *clk;

    int irqs[IPCC_IRQ_NUM];

    int wkp;

    u32 proc_id;

    u32 n_chans;

    u32 xcr;

    u32 xmr;

};

​

static inline void stm32_ipcc_set_bits(void __iomem *reg, u32 mask)

{

    writel_relaxed(readl_relaxed(reg) | mask, reg);