linux-imx

/*

 * OKI Semiconductor ML86V7667 video decoder driver

 *

 * Author: Vladimir Barinov <source@cogentembedded.com>

 * Copyright (C) 2013 Cogent Embedded, Inc.

 * Copyright (C) 2013 Renesas Solutions Corp.

 *

 * This program is free software; you can redistribute  it and/or modify it

 * under  the terms of  the GNU General  Public License as published by the

 * Free Software Foundation;  either version 2 of the  License, or (at your

 * option) any later version.

 */

​

#include <linux/init.h>

#include <linux/module.h>

#include <linux/i2c.h>

#include <linux/slab.h>

#include <linux/videodev2.h>

#include <media/v4l2-subdev.h>

#include <media/v4l2-device.h>

#include <media/v4l2-ioctl.h>

#include <media/v4l2-ctrls.h>

​

#define DRV_NAME "ml86v7667"

​

/* Subaddresses */

#define MRA_REG         0x00 /* Mode Register A */

#define MRC_REG         0x02 /* Mode Register C */

#define LUMC_REG        0x0C /* Luminance Control */

#define CLC_REG         0x10 /* Contrast level control */

#define SSEPL_REG       0x11 /* Sync separation level */

#define CHRCA_REG       0x12 /* Chrominance Control A */

#define ACCC_REG        0x14 /* ACC Loop filter & Chrominance control */

#define ACCRC_REG       0x15 /* ACC Reference level control */

#define HUE_REG         0x16 /* Hue control */

#define ADC2_REG        0x1F /* ADC Register 2 */

#define PLLR1_REG       0x20 /* PLL Register 1 */

#define STATUS_REG      0x2C /* STATUS Register */

​

/* Mode Register A register bits */

#define MRA_OUTPUT_MODE_MASK    (3 << 6)

#define MRA_ITUR_BT601      (1 << 6)

#define MRA_ITUR_BT656      (0 << 6)

#define MRA_INPUT_MODE_MASK (7 << 3)

#define MRA_PAL_BT601       (4 << 3)

#define MRA_NTSC_BT601      (0 << 3)

#define MRA_REGISTER_MODE   (1 << 0)

​

/* Mode Register C register bits */

#define MRC_AUTOSELECT      (1 << 7)

​

/* Luminance Control register bits */

#define LUMC_ONOFF_SHIFT    7

#define LUMC_ONOFF_MASK     (1 << 7)

​

/* Contrast level control register bits */

#define CLC_CONTRAST_ONOFF  (1 << 7)

#define CLC_CONTRAST_MASK   0x0F

​

/* Sync separation level register bits */

#define SSEPL_LUMINANCE_ONOFF   (1 << 7)

#define SSEPL_LUMINANCE_MASK    0x7F

​