linux-imx

/*

 * Copyright (C) 2015 - 2016 Samsung Electronics Co., Ltd.

 *

 * Authors: Inha Song <ideal.song@samsung.com>

 *          Sylwester Nawrocki <s.nawrocki@samsung.com>

 *

 * Samsung Exynos SoC series Low Power Audio Subsystem driver.

 *

 * This module provides regmap for the Top SFR region and instantiates

 * devices for IP blocks like DMAC, I2S, UART.

 *

 * This program is free software; you can redistribute it and/or modify

 * it under the terms of the GNU General Public License version 2 and

 * only version 2 as published by the Free Software Foundation.

 */

​

#include <linux/clk.h>

#include <linux/delay.h>

#include <linux/io.h>

#include <linux/module.h>

#include <linux/mfd/syscon.h>

#include <linux/of.h>

#include <linux/of_platform.h>

#include <linux/platform_device.h>

#include <linux/pm_runtime.h>

#include <linux/regmap.h>

#include <linux/soc/samsung/exynos-regs-pmu.h>

#include <linux/types.h>

​

/* LPASS Top register definitions */

#define SFR_LPASS_CORE_SW_RESET     0x08

#define  LPASS_SB_SW_RESET      BIT(11)

#define  LPASS_UART_SW_RESET        BIT(10)

#define  LPASS_PCM_SW_RESET     BIT(9)

#define  LPASS_I2S_SW_RESET     BIT(8)

#define  LPASS_WDT1_SW_RESET        BIT(4)

#define  LPASS_WDT0_SW_RESET        BIT(3)

#define  LPASS_TIMER_SW_RESET       BIT(2)

#define  LPASS_MEM_SW_RESET     BIT(1)

#define  LPASS_DMA_SW_RESET     BIT(0)

​

#define SFR_LPASS_INTR_CA5_MASK     0x48

#define SFR_LPASS_INTR_CPU_MASK     0x58

#define  LPASS_INTR_APM         BIT(9)

#define  LPASS_INTR_MIF         BIT(8)

#define  LPASS_INTR_TIMER       BIT(7)

#define  LPASS_INTR_DMA         BIT(6)

#define  LPASS_INTR_GPIO        BIT(5)

#define  LPASS_INTR_I2S         BIT(4)

#define  LPASS_INTR_PCM         BIT(3)

#define  LPASS_INTR_SLIMBUS     BIT(2)

#define  LPASS_INTR_UART        BIT(1)

#define  LPASS_INTR_SFR         BIT(0)

​

struct exynos_lpass {

    /* pointer to the LPASS TOP regmap */

    struct regmap *top;

    struct clk *sfr0_clk;

};

​

static void exynos_lpass_core_sw_reset(struct exynos_lpass *lpass, int mask)

{

    unsigned int val = 0;

​

    regmap_read(lpass->top, SFR_LPASS_CORE_SW_RESET, &val);

​

    val &= ~mask;

    regmap_write(lpass->top, SFR_LPASS_CORE_SW_RESET, val);

​

    usleep_range(100, 150);

​

    val |= mask;

    regmap_write(lpass->top, SFR_LPASS_CORE_SW_RESET, val);

}

​

static void exynos_lpass_enable(struct exynos_lpass *lpass)

{

    clk_prepare_enable(lpass->sfr0_clk);

​

    /* Unmask SFR, DMA and I2S interrupt */

    regmap_write(lpass->top, SFR_LPASS_INTR_CA5_MASK,

             LPASS_INTR_SFR | LPASS_INTR_DMA | LPASS_INTR_I2S);

​

    regmap_write(lpass->top, SFR_LPASS_INTR_CPU_MASK,

             LPASS_INTR_SFR | LPASS_INTR_DMA | LPASS_INTR_I2S |

             LPASS_INTR_UART);

​

    exynos_lpass_core_sw_reset(lpass, LPASS_I2S_SW_RESET);

    exynos_lpass_core_sw_reset(lpass, LPASS_DMA_SW_RESET);

    exynos_lpass_core_sw_reset(lpass, LPASS_MEM_SW_RESET);

    exynos_lpass_core_sw_reset(lpass, LPASS_UART_SW_RESET);

}