linux-imx

/*

 * Maxim MAX77620 MFD Driver

 *

 * Copyright (C) 2016 NVIDIA CORPORATION. All rights reserved.

 *

 * Author:

 *  Laxman Dewangan <ldewangan@nvidia.com>

 *  Chaitanya Bandi <bandik@nvidia.com>

 *  Mallikarjun Kasoju <mkasoju@nvidia.com>

 *

 * This program is free software; you can redistribute it and/or modify

 * it under the terms of the GNU General Public License version 2 as

 * published by the Free Software Foundation.

 */

​

/****************** Teminology used in driver ********************

 * Here are some terminology used from datasheet for quick reference:

 * Flexible Power Sequence (FPS):

 * The Flexible Power Sequencer (FPS) allows each regulator to power up under

 * hardware or software control. Additionally, each regulator can power on

 * independently or among a group of other regulators with an adjustable

 * power-up and power-down delays (sequencing). GPIO1, GPIO2, and GPIO3 can

 * be programmed to be part of a sequence allowing external regulators to be

 * sequenced along with internal regulators. 32KHz clock can be programmed to

 * be part of a sequence.

 * There is 3 FPS confguration registers and all resources are configured to

 * any of these FPS or no FPS.

 */

​

#include <linux/i2c.h>

#include <linux/interrupt.h>

#include <linux/mfd/core.h>

#include <linux/mfd/max77620.h>

#include <linux/init.h>

#include <linux/of.h>

#include <linux/of_device.h>

#include <linux/regmap.h>

#include <linux/slab.h>

​

static const struct resource gpio_resources[] = {

    DEFINE_RES_IRQ(MAX77620_IRQ_TOP_GPIO),

};

​

static const struct resource power_resources[] = {

    DEFINE_RES_IRQ(MAX77620_IRQ_LBT_MBATLOW),

};

​

static const struct resource rtc_resources[] = {

    DEFINE_RES_IRQ(MAX77620_IRQ_TOP_RTC),

};

​

static const struct resource thermal_resources[] = {

    DEFINE_RES_IRQ(MAX77620_IRQ_LBT_TJALRM1),

    DEFINE_RES_IRQ(MAX77620_IRQ_LBT_TJALRM2),

};

​

static const struct regmap_irq max77620_top_irqs[] = {

    REGMAP_IRQ_REG(MAX77620_IRQ_TOP_GLBL, 0, MAX77620_IRQ_TOP_GLBL_MASK),

    REGMAP_IRQ_REG(MAX77620_IRQ_TOP_SD, 0, MAX77620_IRQ_TOP_SD_MASK),

    REGMAP_IRQ_REG(MAX77620_IRQ_TOP_LDO, 0, MAX77620_IRQ_TOP_LDO_MASK),

    REGMAP_IRQ_REG(MAX77620_IRQ_TOP_GPIO, 0, MAX77620_IRQ_TOP_GPIO_MASK),

    REGMAP_IRQ_REG(MAX77620_IRQ_TOP_RTC, 0, MAX77620_IRQ_TOP_RTC_MASK),

    REGMAP_IRQ_REG(MAX77620_IRQ_TOP_32K, 0, MAX77620_IRQ_TOP_32K_MASK),

    REGMAP_IRQ_REG(MAX77620_IRQ_TOP_ONOFF, 0, MAX77620_IRQ_TOP_ONOFF_MASK),

    REGMAP_IRQ_REG(MAX77620_IRQ_LBT_MBATLOW, 1, MAX77620_IRQ_LBM_MASK),

    REGMAP_IRQ_REG(MAX77620_IRQ_LBT_TJALRM1, 1, MAX77620_IRQ_TJALRM1_MASK),

    REGMAP_IRQ_REG(MAX77620_IRQ_LBT_TJALRM2, 1, MAX77620_IRQ_TJALRM2_MASK),

};

​

static const struct mfd_cell max77620_children[] = {

    { .name = "max77620-pinctrl", },

    { .name = "max77620-clock", },

    { .name = "max77620-pmic", },

    { .name = "max77620-watchdog", },

    {

        .name = "max77620-gpio",

        .resources = gpio_resources,

        .num_resources = ARRAY_SIZE(gpio_resources),

    }, {

        .name = "max77620-rtc",

        .resources = rtc_resources,

        .num_resources = ARRAY_SIZE(rtc_resources),

    }, {

        .name = "max77620-power",

        .resources = power_resources,

        .num_resources = ARRAY_SIZE(power_resources),

    }, {

        .name = "max77620-thermal",

        .resources = thermal_resources,

        .num_resources = ARRAY_SIZE(thermal_resources),

    },

};