Source of palmas.c - linux-imx - PHYTEC BitBucket (Stash)

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// SPDX-License-Identifier: GPL-2.0-or-later
/*
 * TI Palmas MFD Driver
 *
 * Copyright 2011-2012 Texas Instruments Inc.
 *
 * Author: Graeme Gregory <gg@slimlogic.co.uk>
 */
​
#include <linux/module.h>
#include <linux/moduleparam.h>
#include <linux/init.h>
#include <linux/slab.h>
#include <linux/i2c.h>
#include <linux/interrupt.h>
#include <linux/irq.h>
#include <linux/regmap.h>
#include <linux/err.h>
#include <linux/mfd/core.h>
#include <linux/mfd/palmas.h>
#include <linux/of_device.h>
​
static const struct regmap_config palmas_regmap_config[PALMAS_NUM_CLIENTS] = {
    {
        .reg_bits = 8,
        .val_bits = 8,
        .max_register = PALMAS_BASE_TO_REG(PALMAS_PU_PD_OD_BASE,
                    PALMAS_PRIMARY_SECONDARY_PAD3),
    },
    {
        .reg_bits = 8,
        .val_bits = 8,
        .max_register = PALMAS_BASE_TO_REG(PALMAS_GPADC_BASE,
                    PALMAS_GPADC_SMPS_VSEL_MONITORING),
    },
    {
        .reg_bits = 8,
        .val_bits = 8,
        .max_register = PALMAS_BASE_TO_REG(PALMAS_TRIM_GPADC_BASE,
                    PALMAS_GPADC_TRIM16),
    },
};
​
static const struct regmap_irq tps65917_irqs[] = {
    /* INT1 IRQs */
    [TPS65917_RESERVED1] = {
        .mask = TPS65917_RESERVED,
    },
    [TPS65917_PWRON_IRQ] = {
        .mask = TPS65917_INT1_STATUS_PWRON,
    },
    [TPS65917_LONG_PRESS_KEY_IRQ] = {
        .mask = TPS65917_INT1_STATUS_LONG_PRESS_KEY,
    },
    [TPS65917_RESERVED2] = {
        .mask = TPS65917_RESERVED,
    },
    [TPS65917_PWRDOWN_IRQ] = {
        .mask = TPS65917_INT1_STATUS_PWRDOWN,
    },
    [TPS65917_HOTDIE_IRQ] = {
        .mask = TPS65917_INT1_STATUS_HOTDIE,
    },
    [TPS65917_VSYS_MON_IRQ] = {
        .mask = TPS65917_INT1_STATUS_VSYS_MON,
    },
    [TPS65917_RESERVED3] = {
        .mask = TPS65917_RESERVED,
    },
    /* INT2 IRQs*/
    [TPS65917_RESERVED4] = {
        .mask = TPS65917_RESERVED,
        .reg_offset = 1,
    },
    [TPS65917_OTP_ERROR_IRQ] = {
        .mask = TPS65917_INT2_STATUS_OTP_ERROR,
        .reg_offset = 1,
    },
    [TPS65917_WDT_IRQ] = {
        .mask = TPS65917_INT2_STATUS_WDT,
        .reg_offset = 1,
    },
    [TPS65917_RESERVED5] = {
        .mask = TPS65917_RESERVED,
        .reg_offset = 1,
    },
    [TPS65917_RESET_IN_IRQ] = {
        .mask = TPS65917_INT2_STATUS_RESET_IN,
        .reg_offset = 1,
    },
    [TPS65917_FSD_IRQ] = {
        .mask = TPS65917_INT2_STATUS_FSD,