linux-imx

// SPDX-License-Identifier: GPL-2.0

/*

 * Copyright (C) STMicroelectronics 2016

 * Author: Benjamin Gaignard <benjamin.gaignard@st.com>

 */

​

#include <linux/bitfield.h>

#include <linux/mfd/stm32-timers.h>

#include <linux/module.h>

#include <linux/of_platform.h>

#include <linux/reset.h>

​

#define STM32_TIMERS_MAX_REGISTERS  0x3fc

​

/* DIER register DMA enable bits */

static const u32 stm32_timers_dier_dmaen[STM32_TIMERS_MAX_DMAS] = {

    TIM_DIER_CC1DE,

    TIM_DIER_CC2DE,

    TIM_DIER_CC3DE,

    TIM_DIER_CC4DE,

    TIM_DIER_UIE,

    TIM_DIER_TDE,

    TIM_DIER_COMDE

};

​

static void stm32_timers_dma_done(void *p)

{

    struct stm32_timers_dma *dma = p;

    struct dma_tx_state state;

    enum dma_status status;

​

    status = dmaengine_tx_status(dma->chan, dma->chan->cookie, &state);

    if (status == DMA_COMPLETE)

        complete(&dma->completion);

}

​

/**

 * stm32_timers_dma_burst_read - Read from timers registers using DMA.

 *

 * Read from STM32 timers registers using DMA on a single event.

 * @dev: reference to stm32_timers MFD device

 * @buf: DMA'able destination buffer

 * @id: stm32_timers_dmas event identifier (ch[1..4], up, trig or com)

 * @reg: registers start offset for DMA to read from (like CCRx for capture)

 * @num_reg: number of registers to read upon each DMA request, starting @reg.

 * @bursts: number of bursts to read (e.g. like two for pwm period capture)

 * @tmo_ms: timeout (milliseconds)

 */

int stm32_timers_dma_burst_read(struct device *dev, u32 *buf,

                enum stm32_timers_dmas id, u32 reg,

                unsigned int num_reg, unsigned int bursts,

                unsigned long tmo_ms)

{

    struct stm32_timers *ddata = dev_get_drvdata(dev);

    unsigned long timeout = msecs_to_jiffies(tmo_ms);

    struct regmap *regmap = ddata->regmap;

    struct stm32_timers_dma *dma = &ddata->dma;

    size_t len = num_reg * bursts * sizeof(u32);

    struct dma_async_tx_descriptor *desc;

    struct dma_slave_config config;

    dma_cookie_t cookie;

    dma_addr_t dma_buf;

    u32 dbl, dba;

    long err;

    int ret;

​

    /* Sanity check */

    if (id < STM32_TIMERS_DMA_CH1 || id >= STM32_TIMERS_MAX_DMAS)

        return -EINVAL;

​

    if (!num_reg || !bursts || reg > STM32_TIMERS_MAX_REGISTERS ||

        (reg + num_reg * sizeof(u32)) > STM32_TIMERS_MAX_REGISTERS)

        return -EINVAL;

​

    if (!dma->chans[id])

        return -ENODEV;

    mutex_lock(&dma->lock);

​

    /* Select DMA channel in use */

    dma->chan = dma->chans[id];

    dma_buf = dma_map_single(dev, buf, len, DMA_FROM_DEVICE);

    if (dma_mapping_error(dev, dma_buf)) {

        ret = -ENOMEM;

        goto unlock;

    }

​

    /* Prepare DMA read from timer registers, using DMA burst mode */

    memset(&config, 0, sizeof(config));

    config.src_addr = (dma_addr_t)dma->phys_base + TIM_DMAR;

    config.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;

    ret = dmaengine_slave_config(dma->chan, &config);

    if (ret)