linux-imx

/*

 * Toshiba TC6393XB SoC support

 *

 * Copyright(c) 2005-2006 Chris Humbert

 * Copyright(c) 2005 Dirk Opfer

 * Copyright(c) 2005 Ian Molton <spyro@f2s.com>

 * Copyright(c) 2007 Dmitry Baryshkov

 *

 * Based on code written by Sharp/Lineo for 2.4 kernels

 * Based on locomo.c

 *

 * This program is free software; you can redistribute it and/or modify

 * it under the terms of the GNU General Public License version 2 as

 * published by the Free Software Foundation.

 */

​

#include <linux/kernel.h>

#include <linux/module.h>

#include <linux/io.h>

#include <linux/irq.h>

#include <linux/platform_device.h>

#include <linux/clk.h>

#include <linux/err.h>

#include <linux/mfd/core.h>

#include <linux/mfd/tmio.h>

#include <linux/mfd/tc6393xb.h>

#include <linux/gpio/driver.h>

#include <linux/slab.h>

​

#define SCR_REVID   0x08        /* b Revision ID    */

#define SCR_ISR     0x50        /* b Interrupt Status   */

#define SCR_IMR     0x52        /* b Interrupt Mask */

#define SCR_IRR     0x54        /* b Interrupt Routing  */

#define SCR_GPER    0x60        /* w GP Enable      */

#define SCR_GPI_SR(i)   (0x64 + (i))    /* b3 GPI Status    */

#define SCR_GPI_IMR(i)  (0x68 + (i))    /* b3 GPI INT Mask  */

#define SCR_GPI_EDER(i) (0x6c + (i))    /* b3 GPI Edge Detect Enable */

#define SCR_GPI_LIR(i)  (0x70 + (i))    /* b3 GPI Level Invert  */

#define SCR_GPO_DSR(i)  (0x78 + (i))    /* b3 GPO Data Set  */

#define SCR_GPO_DOECR(i) (0x7c + (i))   /* b3 GPO Data OE Control */

#define SCR_GP_IARCR(i) (0x80 + (i))    /* b3 GP Internal Active Register Control */

#define SCR_GP_IARLCR(i) (0x84 + (i))   /* b3 GP INTERNAL Active Register Level Control */

#define SCR_GPI_BCR(i)  (0x88 + (i))    /* b3 GPI Buffer Control */

#define SCR_GPA_IARCR   0x8c        /* w GPa Internal Active Register Control */

#define SCR_GPA_IARLCR  0x90        /* w GPa Internal Active Register Level Control */

#define SCR_GPA_BCR 0x94        /* w GPa Buffer Control */

#define SCR_CCR     0x98        /* w Clock Control  */

#define SCR_PLL2CR  0x9a        /* w PLL2 Control   */

#define SCR_PLL1CR  0x9c        /* l PLL1 Control   */

#define SCR_DIARCR  0xa0        /* b Device Internal Active Register Control */

#define SCR_DBOCR   0xa1        /* b Device Buffer Off Control */

#define SCR_FER     0xe0        /* b Function Enable    */

#define SCR_MCR     0xe4        /* w Mode Control   */

#define SCR_CONFIG  0xfc        /* b Configuration Control */

#define SCR_DEBUG   0xff        /* b Debug      */

​

#define SCR_CCR_CK32K   BIT(0)

#define SCR_CCR_USBCK   BIT(1)

#define SCR_CCR_UNK1    BIT(4)

#define SCR_CCR_MCLK_MASK   (7 << 8)

#define SCR_CCR_MCLK_OFF    (0 << 8)

#define SCR_CCR_MCLK_12 (1 << 8)

#define SCR_CCR_MCLK_24 (2 << 8)