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committed a205425658d * which module is generating the interrupt request. However, we can't do i2c/* * twl4030-irq.c - TWL4030/TPS659x0 irq support * * Copyright (C) 2005-2006 Texas Instruments, Inc. * * Modifications to defer interrupt handling to a kernel thread: * Copyright (C) 2006 MontaVista Software, Inc. * * Based on tlv320aic23.c: * Copyright (c) by Kai Svahn <kai.svahn@nokia.com> * * Code cleanup and modifications to IRQ handler. * by syed khasim <x0khasim@ti.com> * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; either version 2 of the License, or * (at your option) any later version. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA *//* * TWL4030 IRQ handling has two stages in hardware, and thus in software. * The Primary Interrupt Handler (PIH) stage exposes status bits saying * which Secondary Interrupt Handler (SIH) stage is raising an interrupt. * SIH modules are more traditional IRQ components, which support per-IRQ * enable/disable and trigger controls; they do most of the work. * * These chips are designed to support IRQ handling from two different * I2C masters. Each has a dedicated IRQ line, and dedicated IRQ status * and mask registers in the PIH and SIH modules. * * We set up IRQs starting at a platform-specified base, always starting * with PIH and the SIH for PWR_INT and then usually adding GPIO: * base + 0 .. base + 7 PIH * base + 8 .. base + 15 SIH for PWR_INT * base + 16 .. base + 33 SIH for GPIO *//* PIH register offsets *//* for testing */