linux-imx

/*

 *

 * Handle TWL4030 Power initialization

 *

 * Copyright (C) 2008 Nokia Corporation

 * Copyright (C) 2006 Texas Instruments, Inc

 *

 * Written by   Kalle Jokiniemi

 *      Peter De Schrijver <peter.de-schrijver@nokia.com>

 * Several fixes by Amit Kucheria <amit.kucheria@verdurent.com>

 *

 * This file is subject to the terms and conditions of the GNU General

 * Public License. See the file "COPYING" in the main directory of this

 * archive for more details.

 *

 * This program is distributed in the hope that it will be useful,

 * but WITHOUT ANY WARRANTY; without even the implied warranty of

 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the

 * GNU General Public License for more details.

 *

 * You should have received a copy of the GNU General Public License

 * along with this program; if not, write to the Free Software

 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA

 */

​

#include <linux/module.h>

#include <linux/pm.h>

#include <linux/mfd/twl.h>

#include <linux/platform_device.h>

#include <linux/of.h>

#include <linux/of_device.h>

​

#include <asm/mach-types.h>

​

static u8 twl4030_start_script_address = 0x2b;

​

/* Register bits for P1, P2 and P3_SW_EVENTS */

#define PWR_STOPON_PRWON    BIT(6)

#define PWR_STOPON_SYSEN    BIT(5)

#define PWR_ENABLE_WARMRESET    BIT(4)

#define PWR_LVL_WAKEUP      BIT(3)

#define PWR_DEVACT      BIT(2)

#define PWR_DEVSLP      BIT(1)

#define PWR_DEVOFF      BIT(0)

​

/* Register bits for CFG_P1_TRANSITION (also for P2 and P3) */

#define STARTON_SWBUG       BIT(7)  /* Start on watchdog */

#define STARTON_VBUS        BIT(5)  /* Start on VBUS */

#define STARTON_VBAT        BIT(4)  /* Start on battery insert */

#define STARTON_RTC     BIT(3)  /* Start on RTC */

#define STARTON_USB     BIT(2)  /* Start on USB host */

#define STARTON_CHG     BIT(1)  /* Start on charger */

#define STARTON_PWON        BIT(0)  /* Start on PWRON button */

​

#define SEQ_OFFSYNC     (1 << 0)

​

#define PHY_TO_OFF_PM_MASTER(p)     (p - 0x36)

#define PHY_TO_OFF_PM_RECEIVER(p)   (p - 0x5b)

​

/* resource - hfclk */

#define R_HFCLKOUT_DEV_GRP  PHY_TO_OFF_PM_RECEIVER(0xe6)

​

/* PM events */

#define R_P1_SW_EVENTS      PHY_TO_OFF_PM_MASTER(0x46)

#define R_P2_SW_EVENTS      PHY_TO_OFF_PM_MASTER(0x47)

#define R_P3_SW_EVENTS      PHY_TO_OFF_PM_MASTER(0x48)

#define R_CFG_P1_TRANSITION PHY_TO_OFF_PM_MASTER(0x36)

#define R_CFG_P2_TRANSITION PHY_TO_OFF_PM_MASTER(0x37)

#define R_CFG_P3_TRANSITION PHY_TO_OFF_PM_MASTER(0x38)

​

#define END_OF_SCRIPT       0x3f

​

#define R_SEQ_ADD_A2S       PHY_TO_OFF_PM_MASTER(0x55)

#define R_SEQ_ADD_S2A12     PHY_TO_OFF_PM_MASTER(0x56)

#define R_SEQ_ADD_S2A3      PHY_TO_OFF_PM_MASTER(0x57)

#define R_SEQ_ADD_WARM      PHY_TO_OFF_PM_MASTER(0x58)

#define R_MEMORY_ADDRESS    PHY_TO_OFF_PM_MASTER(0x59)

#define R_MEMORY_DATA       PHY_TO_OFF_PM_MASTER(0x5a)

​

/* resource configuration registers

   <RESOURCE>_DEV_GRP   at address 'n+0'

   <RESOURCE>_TYPE      at address 'n+1'

   <RESOURCE>_REMAP     at address 'n+2'

   <RESOURCE>_DEDICATED at address 'n+3'

*/

#define DEV_GRP_OFFSET      0

#define TYPE_OFFSET     1

#define REMAP_OFFSET        2

#define DEDICATED_OFFSET    3

​

/* Bit positions in the registers */

​