linux-imx

/**

 * Host side test driver to test endpoint functionality

 *

 * Copyright (C) 2017 Texas Instruments

 * Author: Kishon Vijay Abraham I <kishon@ti.com>

 *

 * This program is free software: you can redistribute it and/or modify

 * it under the terms of the GNU General Public License version 2 of

 * the License as published by the Free Software Foundation.

 *

 * This program is distributed in the hope that it will be useful,

 * but WITHOUT ANY WARRANTY; without even the implied warranty of

 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the

 * GNU General Public License for more details.

 *

 * You should have received a copy of the GNU General Public License

 * along with this program.  If not, see <http://www.gnu.org/licenses/>.

 */

​

#include <linux/crc32.h>

#include <linux/delay.h>

#include <linux/fs.h>

#include <linux/io.h>

#include <linux/interrupt.h>

#include <linux/irq.h>

#include <linux/miscdevice.h>

#include <linux/module.h>

#include <linux/mutex.h>

#include <linux/random.h>

#include <linux/slab.h>

#include <linux/pci.h>

#include <linux/pci_ids.h>

​

#include <linux/pci_regs.h>

​

#include <uapi/linux/pcitest.h>

​

#define DRV_MODULE_NAME             "pci-endpoint-test"

​

#define IRQ_TYPE_UNDEFINED          -1

#define IRQ_TYPE_LEGACY             0

#define IRQ_TYPE_MSI                1

#define IRQ_TYPE_MSIX               2

​

#define PCI_ENDPOINT_TEST_MAGIC         0x0

​

#define PCI_ENDPOINT_TEST_COMMAND       0x4

#define COMMAND_RAISE_LEGACY_IRQ        BIT(0)

#define COMMAND_RAISE_MSI_IRQ           BIT(1)

#define COMMAND_RAISE_MSIX_IRQ          BIT(2)

#define COMMAND_READ                BIT(3)

#define COMMAND_WRITE               BIT(4)

#define COMMAND_COPY                BIT(5)

​

#define PCI_ENDPOINT_TEST_STATUS        0x8

#define STATUS_READ_SUCCESS         BIT(0)

#define STATUS_READ_FAIL            BIT(1)

#define STATUS_WRITE_SUCCESS            BIT(2)

#define STATUS_WRITE_FAIL           BIT(3)

#define STATUS_COPY_SUCCESS         BIT(4)

#define STATUS_COPY_FAIL            BIT(5)

#define STATUS_IRQ_RAISED           BIT(6)

#define STATUS_SRC_ADDR_INVALID         BIT(7)

#define STATUS_DST_ADDR_INVALID         BIT(8)

​

#define PCI_ENDPOINT_TEST_LOWER_SRC_ADDR    0x0c

#define PCI_ENDPOINT_TEST_UPPER_SRC_ADDR    0x10

​

#define PCI_ENDPOINT_TEST_LOWER_DST_ADDR    0x14

#define PCI_ENDPOINT_TEST_UPPER_DST_ADDR    0x18

​

#define PCI_ENDPOINT_TEST_SIZE          0x1c

#define PCI_ENDPOINT_TEST_CHECKSUM      0x20

​

#define PCI_ENDPOINT_TEST_IRQ_TYPE      0x24

#define PCI_ENDPOINT_TEST_IRQ_NUMBER        0x28

​

static DEFINE_IDA(pci_endpoint_test_ida);

​

#define to_endpoint_test(priv) container_of((priv), struct pci_endpoint_test, \

                        miscdev)

​

static bool no_msi;

module_param(no_msi, bool, 0444);

MODULE_PARM_DESC(no_msi, "Disable MSI interrupt in pci_endpoint_test");

​

static int irq_type = IRQ_TYPE_MSI;

module_param(irq_type, int, 0444);

MODULE_PARM_DESC(irq_type, "IRQ mode selection in pci_endpoint_test (0 - Legacy, 1 - MSI, 2 - MSI-X)");

​

enum pci_barno {

    BAR_0,