#include <linux/bitfield.h>
#include <linux/bitops.h>
#include <linux/iopoll.h>
#include <linux/module.h>
#include <linux/nvmem-provider.h>
#include <linux/of_device.h>
#include <linux/platform_device.h>
#define MESON_MX_EFUSE_CNTL1 0x04
#define MESON_MX_EFUSE_CNTL1_PD_ENABLE BIT(27)
#define MESON_MX_EFUSE_CNTL1_AUTO_RD_BUSY BIT(26)
#define MESON_MX_EFUSE_CNTL1_AUTO_RD_START BIT(25)
#define MESON_MX_EFUSE_CNTL1_AUTO_RD_ENABLE BIT(24)
#define MESON_MX_EFUSE_CNTL1_BYTE_WR_DATA GENMASK(23, 16)
#define MESON_MX_EFUSE_CNTL1_AUTO_WR_BUSY BIT(14)
#define MESON_MX_EFUSE_CNTL1_AUTO_WR_START BIT(13)
#define MESON_MX_EFUSE_CNTL1_AUTO_WR_ENABLE BIT(12)
#define MESON_MX_EFUSE_CNTL1_BYTE_ADDR_SET BIT(11)
#define MESON_MX_EFUSE_CNTL1_BYTE_ADDR_MASK GENMASK(10, 0)
#define MESON_MX_EFUSE_CNTL2 0x08
#define MESON_MX_EFUSE_CNTL4 0x10
#define MESON_MX_EFUSE_CNTL4_ENCRYPT_ENABLE BIT(10)
struct meson_mx_efuse_platform_data {
struct nvmem_device *nvmem;
struct nvmem_config config;
static void meson_mx_efuse_mask_bits(struct meson_mx_efuse *efuse, u32 reg,
data = readl(efuse->base + reg);
writel(data, efuse->base + reg);
static int meson_mx_efuse_hw_enable(struct meson_mx_efuse *efuse)