linux-imx

// SPDX-License-Identifier: GPL-2.0

// Copyright (C) 2018 Spreadtrum Communications Inc.

​

#include <linux/hwspinlock.h>

#include <linux/module.h>

#include <linux/of.h>

#include <linux/platform_device.h>

#include <linux/regmap.h>

#include <linux/nvmem-provider.h>

​

/* PMIC global registers definition */

#define SC27XX_MODULE_EN        0xc08

#define SC27XX_EFUSE_EN         BIT(6)

​

/* Efuse controller registers definition */

#define SC27XX_EFUSE_GLB_CTRL       0x0

#define SC27XX_EFUSE_DATA_RD        0x4

#define SC27XX_EFUSE_DATA_WR        0x8

#define SC27XX_EFUSE_BLOCK_INDEX    0xc

#define SC27XX_EFUSE_MODE_CTRL      0x10

#define SC27XX_EFUSE_STATUS     0x14

#define SC27XX_EFUSE_WR_TIMING_CTRL 0x20

#define SC27XX_EFUSE_RD_TIMING_CTRL 0x24

#define SC27XX_EFUSE_EFUSE_DEB_CTRL 0x28

​

/* Mask definition for SC27XX_EFUSE_BLOCK_INDEX register */

#define SC27XX_EFUSE_BLOCK_MASK     GENMASK(4, 0)

​

/* Bits definitions for SC27XX_EFUSE_MODE_CTRL register */

#define SC27XX_EFUSE_PG_START       BIT(0)

#define SC27XX_EFUSE_RD_START       BIT(1)

#define SC27XX_EFUSE_CLR_RDDONE     BIT(2)

​

/* Bits definitions for SC27XX_EFUSE_STATUS register */

#define SC27XX_EFUSE_PGM_BUSY       BIT(0)

#define SC27XX_EFUSE_READ_BUSY      BIT(1)

#define SC27XX_EFUSE_STANDBY        BIT(2)

#define SC27XX_EFUSE_GLOBAL_PROT    BIT(3)

#define SC27XX_EFUSE_RD_DONE        BIT(4)

​

/* Block number and block width (bytes) definitions */

#define SC27XX_EFUSE_BLOCK_MAX      32

#define SC27XX_EFUSE_BLOCK_WIDTH    2

​

/* Timeout (ms) for the trylock of hardware spinlocks */

#define SC27XX_EFUSE_HWLOCK_TIMEOUT 5000

​

/* Timeout (us) of polling the status */

#define SC27XX_EFUSE_POLL_TIMEOUT   3000000

#define SC27XX_EFUSE_POLL_DELAY_US  10000

​

struct sc27xx_efuse {

    struct device *dev;

    struct regmap *regmap;

    struct hwspinlock *hwlock;

    struct mutex mutex;

    u32 base;

};

​

/*

 * On Spreadtrum platform, we have multi-subsystems will access the unique

 * efuse controller, so we need one hardware spinlock to synchronize between

 * the multiple subsystems.