linux-imx

// SPDX-License-Identifier: GPL-2.0

/*

 * Copyright (C) 2015 Broadcom Corporation

 */

​

#include <linux/interrupt.h>

#include <linux/irqchip/chained_irq.h>

#include <linux/irqdomain.h>

#include <linux/msi.h>

#include <linux/of_irq.h>

#include <linux/of_pci.h>

#include <linux/pci.h>

​

#include "pcie-iproc.h"

​

#define IPROC_MSI_INTR_EN_SHIFT        11

#define IPROC_MSI_INTR_EN              BIT(IPROC_MSI_INTR_EN_SHIFT)

#define IPROC_MSI_INT_N_EVENT_SHIFT    1

#define IPROC_MSI_INT_N_EVENT          BIT(IPROC_MSI_INT_N_EVENT_SHIFT)

#define IPROC_MSI_EQ_EN_SHIFT          0

#define IPROC_MSI_EQ_EN                BIT(IPROC_MSI_EQ_EN_SHIFT)

​

#define IPROC_MSI_EQ_MASK              0x3f

​

/* Max number of GIC interrupts */

#define NR_HW_IRQS                     6

​

/* Number of entries in each event queue */

#define EQ_LEN                         64

​

/* Size of each event queue memory region */

#define EQ_MEM_REGION_SIZE             SZ_4K

​

/* Size of each MSI address region */

#define MSI_MEM_REGION_SIZE            SZ_4K

​

enum iproc_msi_reg {

    IPROC_MSI_EQ_PAGE = 0,

    IPROC_MSI_EQ_PAGE_UPPER,

    IPROC_MSI_PAGE,

    IPROC_MSI_PAGE_UPPER,

    IPROC_MSI_CTRL,

    IPROC_MSI_EQ_HEAD,

    IPROC_MSI_EQ_TAIL,

    IPROC_MSI_INTS_EN,

    IPROC_MSI_REG_SIZE,

};

​

struct iproc_msi;

​

/**

 * iProc MSI group

 *

 * One MSI group is allocated per GIC interrupt, serviced by one iProc MSI

 * event queue.

 *

 * @msi: pointer to iProc MSI data

 * @gic_irq: GIC interrupt

 * @eq: Event queue number

 */

struct iproc_msi_grp {

    struct iproc_msi *msi;

    int gic_irq;

    unsigned int eq;

};

​

/**

 * iProc event queue based MSI

 *

 * Only meant to be used on platforms without MSI support integrated into the

 * GIC.

 *

 * @pcie: pointer to iProc PCIe data

 * @reg_offsets: MSI register offsets

 * @grps: MSI groups

 * @nr_irqs: number of total interrupts connected to GIC

 * @nr_cpus: number of toal CPUs

 * @has_inten_reg: indicates the MSI interrupt enable register needs to be

 * set explicitly (required for some legacy platforms)

 * @bitmap: MSI vector bitmap

 * @bitmap_lock: lock to protect access to the MSI bitmap

 * @nr_msi_vecs: total number of MSI vectors

 * @inner_domain: inner IRQ domain

 * @msi_domain: MSI IRQ domain

 * @nr_eq_region: required number of 4K aligned memory region for MSI event

 * queues

 * @nr_msi_region: required number of 4K aligned address region for MSI posted

 * writes

 * @eq_cpu: pointer to allocated memory region for MSI event queues

 * @eq_dma: DMA address of MSI event queues

 * @msi_addr: MSI address

 */