linux-imx

// SPDX-License-Identifier: GPL-2.0+

/*

 * Rockchip AXI PCIe host controller driver

 *

 * Copyright (c) 2016 Rockchip, Inc.

 *

 * Author: Shawn Lin <shawn.lin@rock-chips.com>

 *         Wenrui Li <wenrui.li@rock-chips.com>

 *

 * Bits taken from Synopsys DesignWare Host controller driver and

 * ARM PCI Host generic driver.

 */

​

#include <linux/bitrev.h>

#include <linux/clk.h>

#include <linux/delay.h>

#include <linux/gpio/consumer.h>

#include <linux/init.h>

#include <linux/interrupt.h>

#include <linux/iopoll.h>

#include <linux/irq.h>

#include <linux/irqchip/chained_irq.h>

#include <linux/irqdomain.h>

#include <linux/kernel.h>

#include <linux/mfd/syscon.h>

#include <linux/module.h>

#include <linux/of_address.h>

#include <linux/of_device.h>

#include <linux/of_pci.h>

#include <linux/of_platform.h>

#include <linux/of_irq.h>

#include <linux/pci.h>

#include <linux/pci_ids.h>

#include <linux/phy/phy.h>

#include <linux/platform_device.h>

#include <linux/reset.h>

#include <linux/regmap.h>

​

#include "../pci.h"

#include "pcie-rockchip.h"

​

static void rockchip_pcie_enable_bw_int(struct rockchip_pcie *rockchip)

{

    u32 status;

​

    status = rockchip_pcie_read(rockchip, PCIE_RC_CONFIG_LCS);

    status |= (PCI_EXP_LNKCTL_LBMIE | PCI_EXP_LNKCTL_LABIE);

    rockchip_pcie_write(rockchip, status, PCIE_RC_CONFIG_LCS);

}

​

static void rockchip_pcie_clr_bw_int(struct rockchip_pcie *rockchip)

{

    u32 status;

​

    status = rockchip_pcie_read(rockchip, PCIE_RC_CONFIG_LCS);

    status |= (PCI_EXP_LNKSTA_LBMS | PCI_EXP_LNKSTA_LABS) << 16;

    rockchip_pcie_write(rockchip, status, PCIE_RC_CONFIG_LCS);

}

​

static void rockchip_pcie_update_txcredit_mui(struct rockchip_pcie *rockchip)

{

    u32 val;

​

    /* Update Tx credit maximum update interval */

    val = rockchip_pcie_read(rockchip, PCIE_CORE_TXCREDIT_CFG1);

    val &= ~PCIE_CORE_TXCREDIT_CFG1_MUI_MASK;

    val |= PCIE_CORE_TXCREDIT_CFG1_MUI_ENCODE(24000);   /* ns */

    rockchip_pcie_write(rockchip, val, PCIE_CORE_TXCREDIT_CFG1);

}

​

static int rockchip_pcie_valid_device(struct rockchip_pcie *rockchip,

                      struct pci_bus *bus, int dev)

{

    /* access only one slot on each root port */

    if (bus->number == rockchip->root_bus_nr && dev > 0)

        return 0;

​

    /*

     * do not read more than one device on the bus directly attached

     * to RC's downstream side.

     */

    if (bus->primary == rockchip->root_bus_nr && dev > 0)

        return 0;

​

    return 1;

}

​

static u8 rockchip_pcie_lane_map(struct rockchip_pcie *rockchip)

{

    u32 val;

    u8 map;

​