linux-imx

/*

 * ti113x.h 1.16 1999/10/25 20:03:34

 *

 * The contents of this file are subject to the Mozilla Public License

 * Version 1.1 (the "License"); you may not use this file except in

 * compliance with the License. You may obtain a copy of the License

 * at http://www.mozilla.org/MPL/

 *

 * Software distributed under the License is distributed on an "AS IS"

 * basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See

 * the License for the specific language governing rights and

 * limitations under the License. 

 *

 * The initial developer of the original code is David A. Hinds

 * <dahinds@users.sourceforge.net>.  Portions created by David A. Hinds

 * are Copyright (C) 1999 David A. Hinds.  All Rights Reserved.

 *

 * Alternatively, the contents of this file may be used under the

 * terms of the GNU General Public License version 2 (the "GPL"), in which

 * case the provisions of the GPL are applicable instead of the

 * above.  If you wish to allow the use of your version of this file

 * only under the terms of the GPL and not to allow others to use

 * your version of this file under the MPL, indicate your decision by

 * deleting the provisions above and replace them with the notice and

 * other provisions required by the GPL.  If you do not delete the

 * provisions above, a recipient may use your version of this file

 * under either the MPL or the GPL.

 */

​

#ifndef _LINUX_TI113X_H

#define _LINUX_TI113X_H

​

​

/* Register definitions for TI 113X PCI-to-CardBus bridges */

​

/* System Control Register */

#define TI113X_SYSTEM_CONTROL       0x0080  /* 32 bit */

#define  TI113X_SCR_SMIROUTE        0x04000000

#define  TI113X_SCR_SMISTATUS       0x02000000

#define  TI113X_SCR_SMIENB      0x01000000

#define  TI113X_SCR_VCCPROT     0x00200000

#define  TI113X_SCR_REDUCEZV        0x00100000

#define  TI113X_SCR_CDREQEN     0x00080000

#define  TI113X_SCR_CDMACHAN        0x00070000

#define  TI113X_SCR_SOCACTIVE       0x00002000

#define  TI113X_SCR_PWRSTREAM       0x00000800

#define  TI113X_SCR_DELAYUP     0x00000400

#define  TI113X_SCR_DELAYDOWN       0x00000200

#define  TI113X_SCR_INTERROGATE     0x00000100

#define  TI113X_SCR_CLKRUN_SEL      0x00000080

#define  TI113X_SCR_PWRSAVINGS      0x00000040

#define  TI113X_SCR_SUBSYSRW        0x00000020

#define  TI113X_SCR_CB_DPAR     0x00000010

#define  TI113X_SCR_CDMA_EN     0x00000008

#define  TI113X_SCR_ASYNC_IRQ       0x00000004

#define  TI113X_SCR_KEEPCLK     0x00000002

#define  TI113X_SCR_CLKRUN_ENA      0x00000001  

​

#define  TI122X_SCR_SER_STEP        0xc0000000

#define  TI122X_SCR_INTRTIE     0x20000000

#define  TIXX21_SCR_TIEALL      0x10000000

#define  TI122X_SCR_CBRSVD      0x00400000

#define  TI122X_SCR_MRBURSTDN       0x00008000

#define  TI122X_SCR_MRBURSTUP       0x00004000

#define  TI122X_SCR_RIMUX       0x00000001

​

/* Multimedia Control Register */

#define TI1250_MULTIMEDIA_CTL       0x0084  /* 8 bit */

#define  TI1250_MMC_ZVOUTEN     0x80

#define  TI1250_MMC_PORTSEL     0x40

#define  TI1250_MMC_ZVEN1       0x02

#define  TI1250_MMC_ZVEN0       0x01

​

#define TI1250_GENERAL_STATUS       0x0085  /* 8 bit */

#define TI1250_GPIO0_CONTROL        0x0088  /* 8 bit */

#define TI1250_GPIO1_CONTROL        0x0089  /* 8 bit */

#define TI1250_GPIO2_CONTROL        0x008a  /* 8 bit */

#define TI1250_GPIO3_CONTROL        0x008b  /* 8 bit */

#define TI1250_GPIO_MODE_MASK       0xc0

​

/* IRQMUX/MFUNC Register */

#define TI122X_MFUNC            0x008c  /* 32 bit */

#define TI122X_MFUNC0_MASK      0x0000000f

#define TI122X_MFUNC1_MASK      0x000000f0

#define TI122X_MFUNC2_MASK      0x00000f00

#define TI122X_MFUNC3_MASK      0x0000f000

#define TI122X_MFUNC4_MASK      0x000f0000

#define TI122X_MFUNC5_MASK      0x00f00000

#define TI122X_MFUNC6_MASK      0x0f000000

​

#define TI122X_MFUNC0_INTA      0x00000002

#define TI125X_MFUNC0_INTB      0x00000001