linux-imx

/*

 * ACPI probing code for ARM performance counters.

 *

 * Copyright (C) 2017 ARM Ltd.

 *

 * This program is free software; you can redistribute it and/or modify

 * it under the terms of the GNU General Public License version 2 as

 * published by the Free Software Foundation.

 */

​

#include <linux/acpi.h>

#include <linux/cpumask.h>

#include <linux/init.h>

#include <linux/irq.h>

#include <linux/irqdesc.h>

#include <linux/percpu.h>

#include <linux/perf/arm_pmu.h>

​

#include <asm/cputype.h>

​

static DEFINE_PER_CPU(struct arm_pmu *, probed_pmus);

static DEFINE_PER_CPU(int, pmu_irqs);

​

static int arm_pmu_acpi_register_irq(int cpu)

{

    struct acpi_madt_generic_interrupt *gicc;

    int gsi, trigger;

​

    gicc = acpi_cpu_get_madt_gicc(cpu);

    if (WARN_ON(!gicc))

        return -EINVAL;

​

    gsi = gicc->performance_interrupt;

​

    /*

     * Per the ACPI spec, the MADT cannot describe a PMU that doesn't

     * have an interrupt. QEMU advertises this by using a GSI of zero,

     * which is not known to be valid on any hardware despite being

     * valid per the spec. Take the pragmatic approach and reject a

     * GSI of zero for now.

     */

    if (!gsi)

        return 0;

​

    if (gicc->flags & ACPI_MADT_PERFORMANCE_IRQ_MODE)

        trigger = ACPI_EDGE_SENSITIVE;

    else

        trigger = ACPI_LEVEL_SENSITIVE;

​

    /*

     * Helpfully, the MADT GICC doesn't have a polarity flag for the

     * "performance interrupt". Luckily, on compliant GICs the polarity is

     * a fixed value in HW (for both SPIs and PPIs) that we cannot change

     * from SW.

     *

     * Here we pass in ACPI_ACTIVE_HIGH to keep the core code happy. This

     * may not match the real polarity, but that should not matter.

     *

     * Other interrupt controllers are not supported with ACPI.

     */

    return acpi_register_gsi(NULL, gsi, trigger, ACPI_ACTIVE_HIGH);

}

​

static void arm_pmu_acpi_unregister_irq(int cpu)

{

    struct acpi_madt_generic_interrupt *gicc;

    int gsi;

​

    gicc = acpi_cpu_get_madt_gicc(cpu);

    if (!gicc)

        return;

​

    gsi = gicc->performance_interrupt;

    acpi_unregister_gsi(gsi);

}

​

static int arm_pmu_acpi_parse_irqs(void)

{

    int irq, cpu, irq_cpu, err;

​

    for_each_possible_cpu(cpu) {

        irq = arm_pmu_acpi_register_irq(cpu);

        if (irq < 0) {

            err = irq;

            pr_warn("Unable to parse ACPI PMU IRQ for CPU%d: %d\n",

                cpu, err);

            goto out_err;

        } else if (irq == 0) {

            pr_warn("No ACPI PMU IRQ for CPU%d\n", cpu);

        }

​

        /*