linux-imx

/*

 * Driver for the L3 cache PMUs in Qualcomm Technologies chips.

 *

 * The driver supports a distributed cache architecture where the overall

 * cache for a socket is comprised of multiple slices each with its own PMU.

 * Access to each individual PMU is provided even though all CPUs share all

 * the slices. User space needs to aggregate to individual counts to provide

 * a global picture.

 *

 * See Documentation/perf/qcom_l3_pmu.txt for more details.

 *

 * Copyright (c) 2015-2017, The Linux Foundation. All rights reserved.

 *

 * This program is free software; you can redistribute it and/or modify

 * it under the terms of the GNU General Public License version 2 and

 * only version 2 as published by the Free Software Foundation.

 *

 * This program is distributed in the hope that it will be useful,

 * but WITHOUT ANY WARRANTY; without even the implied warranty of

 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the

 * GNU General Public License for more details.

 */

​

#include <linux/acpi.h>

#include <linux/bitops.h>

#include <linux/interrupt.h>

#include <linux/io.h>

#include <linux/list.h>

#include <linux/module.h>

#include <linux/perf_event.h>

#include <linux/platform_device.h>

​

/*

 * General constants

 */

​

/* Number of counters on each PMU */

#define L3_NUM_COUNTERS  8

/* Mask for the event type field within perf_event_attr.config and EVTYPE reg */

#define L3_EVTYPE_MASK   0xFF

/*

 * Bit position of the 'long counter' flag within perf_event_attr.config.

 * Reserve some space between the event type and this flag to allow expansion

 * in the event type field.

 */

#define L3_EVENT_LC_BIT  32

​

/*

 * Register offsets

 */

​

/* Perfmon registers */

#define L3_HML3_PM_CR       0x000

#define L3_HML3_PM_EVCNTR(__cntr) (0x420 + ((__cntr) & 0x7) * 8)

#define L3_HML3_PM_CNTCTL(__cntr) (0x120 + ((__cntr) & 0x7) * 8)

#define L3_HML3_PM_EVTYPE(__cntr) (0x220 + ((__cntr) & 0x7) * 8)

#define L3_HML3_PM_FILTRA   0x300

#define L3_HML3_PM_FILTRB   0x308

#define L3_HML3_PM_FILTRC   0x310

#define L3_HML3_PM_FILTRAM  0x304

#define L3_HML3_PM_FILTRBM  0x30C

#define L3_HML3_PM_FILTRCM  0x314

​

/* Basic counter registers */

#define L3_M_BC_CR         0x500

#define L3_M_BC_SATROLL_CR 0x504

#define L3_M_BC_CNTENSET   0x508

#define L3_M_BC_CNTENCLR   0x50C

#define L3_M_BC_INTENSET   0x510

#define L3_M_BC_INTENCLR   0x514

#define L3_M_BC_GANG       0x718

#define L3_M_BC_OVSR       0x740

#define L3_M_BC_IRQCTL     0x96C

​

/*

 * Bit field definitions

 */

​

/* L3_HML3_PM_CR */

#define PM_CR_RESET           (0)

​

/* L3_HML3_PM_XCNTCTL/L3_HML3_PM_CNTCTLx */

#define PMCNT_RESET           (0)

​

/* L3_HML3_PM_EVTYPEx */

#define EVSEL(__val)          ((__val) & L3_EVTYPE_MASK)

​

/* Reset value for all the filter registers */

#define PM_FLTR_RESET         (0)

​

/* L3_M_BC_CR */

#define BC_RESET              (1UL << 1)