linux-imx

// SPDX-License-Identifier: GPL-2.0+

/*

 * Copyright (c) 2016 Allwinnertech Co., Ltd.

 * Copyright (C) 2017-2018 Bootlin

 *

 * Maxime Ripard <maxime.ripard@free-electrons.com>

 */

​

#include <linux/bitops.h>

#include <linux/clk.h>

#include <linux/module.h>

#include <linux/of_address.h>

#include <linux/platform_device.h>

#include <linux/regmap.h>

#include <linux/reset.h>

​

#include <linux/phy/phy.h>

#include <linux/phy/phy-mipi-dphy.h>

​

#define SUN6I_DPHY_GCTL_REG     0x00

#define SUN6I_DPHY_GCTL_LANE_NUM(n)     ((((n) - 1) & 3) << 4)

#define SUN6I_DPHY_GCTL_EN          BIT(0)

​

#define SUN6I_DPHY_TX_CTL_REG       0x04

#define SUN6I_DPHY_TX_CTL_HS_TX_CLK_CONT    BIT(28)

​

#define SUN6I_DPHY_TX_TIME0_REG     0x10

#define SUN6I_DPHY_TX_TIME0_HS_TRAIL(n)     (((n) & 0xff) << 24)

#define SUN6I_DPHY_TX_TIME0_HS_PREPARE(n)   (((n) & 0xff) << 16)

#define SUN6I_DPHY_TX_TIME0_LP_CLK_DIV(n)   ((n) & 0xff)

​

#define SUN6I_DPHY_TX_TIME1_REG     0x14

#define SUN6I_DPHY_TX_TIME1_CLK_POST(n)     (((n) & 0xff) << 24)

#define SUN6I_DPHY_TX_TIME1_CLK_PRE(n)      (((n) & 0xff) << 16)

#define SUN6I_DPHY_TX_TIME1_CLK_ZERO(n)     (((n) & 0xff) << 8)

#define SUN6I_DPHY_TX_TIME1_CLK_PREPARE(n)  ((n) & 0xff)

​

#define SUN6I_DPHY_TX_TIME2_REG     0x18

#define SUN6I_DPHY_TX_TIME2_CLK_TRAIL(n)    ((n) & 0xff)

​

#define SUN6I_DPHY_TX_TIME3_REG     0x1c

​

#define SUN6I_DPHY_TX_TIME4_REG     0x20

#define SUN6I_DPHY_TX_TIME4_HS_TX_ANA1(n)   (((n) & 0xff) << 8)

#define SUN6I_DPHY_TX_TIME4_HS_TX_ANA0(n)   ((n) & 0xff)

​

#define SUN6I_DPHY_ANA0_REG     0x4c

#define SUN6I_DPHY_ANA0_REG_PWS         BIT(31)

#define SUN6I_DPHY_ANA0_REG_DMPC        BIT(28)

#define SUN6I_DPHY_ANA0_REG_DMPD(n)     (((n) & 0xf) << 24)

#define SUN6I_DPHY_ANA0_REG_SLV(n)      (((n) & 7) << 12)

#define SUN6I_DPHY_ANA0_REG_DEN(n)      (((n) & 0xf) << 8)

​

#define SUN6I_DPHY_ANA1_REG     0x50

#define SUN6I_DPHY_ANA1_REG_VTTMODE     BIT(31)

#define SUN6I_DPHY_ANA1_REG_CSMPS(n)        (((n) & 3) << 28)

#define SUN6I_DPHY_ANA1_REG_SVTT(n)     (((n) & 0xf) << 24)

​

#define SUN6I_DPHY_ANA2_REG     0x54

#define SUN6I_DPHY_ANA2_EN_P2S_CPU(n)       (((n) & 0xf) << 24)

#define SUN6I_DPHY_ANA2_EN_P2S_CPU_MASK     GENMASK(27, 24)

#define SUN6I_DPHY_ANA2_EN_CK_CPU       BIT(4)

#define SUN6I_DPHY_ANA2_REG_ENIB        BIT(1)