linux-imx

/*

 * AppliedMicro X-Gene Multi-purpose PHY driver

 *

 * Copyright (c) 2014, Applied Micro Circuits Corporation

 * Author: Loc Ho <lho@apm.com>

 *         Tuan Phan <tphan@apm.com>

 *         Suman Tripathi <stripathi@apm.com>

 *

 * This program is free software; you can redistribute  it and/or modify it

 * under  the terms of  the GNU General  Public License as published by the

 * Free Software Foundation;  either version 2 of the  License, or (at your

 * option) any later version.

 *

 * This program is distributed in the hope that it will be useful,

 * but WITHOUT ANY WARRANTY; without even the implied warranty of

 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the

 * GNU General Public License for more details.

 *

 * You should have received a copy of the GNU General Public License

 * along with this program.  If not, see <http://www.gnu.org/licenses/>.

 *

 * The APM X-Gene PHY consists of two PLL clock macro's (CMU) and lanes.

 * The first PLL clock macro is used for internal reference clock. The second

 * PLL clock macro is used to generate the clock for the PHY. This driver

 * configures the first PLL CMU, the second PLL CMU, and programs the PHY to

 * operate according to the mode of operation. The first PLL CMU is only

 * required if internal clock is enabled.

 *

 * Logical Layer Out Of HW module units:

 *

 * -----------------

 * | Internal      |    |------|

 * | Ref PLL CMU   |----|      |     -------------    ---------

 * ------------ ----    | MUX  |-----|PHY PLL CMU|----| Serdes|

 *                      |      |     |           |    ---------

 * External Clock ------|      |     -------------

 *                      |------|

 *

 * The Ref PLL CMU CSR (Configuration System Registers) is accessed

 * indirectly from the SDS offset at 0x2000. It is only required for

 * internal reference clock.

 * The PHY PLL CMU CSR is accessed indirectly from the SDS offset at 0x0000.

 * The Serdes CSR is accessed indirectly from the SDS offset at 0x0400.

 *

 * The Ref PLL CMU can be located within the same PHY IP or outside the PHY IP

 * due to shared Ref PLL CMU. For PHY with Ref PLL CMU shared with another IP,

 * it is located outside the PHY IP. This is the case for the PHY located

 * at 0x1f23a000 (SATA Port 4/5). For such PHY, another resource is required

 * to located the SDS/Ref PLL CMU module and its clock for that IP enabled.

 *

 * Currently, this driver only supports Gen3 SATA mode with external clock.

 */

#include <linux/module.h>

#include <linux/platform_device.h>

#include <linux/io.h>

#include <linux/delay.h>

#include <linux/phy/phy.h>

#include <linux/clk.h>

​

/* Max 2 lanes per a PHY unit */

#define MAX_LANE            2

​

/* Register offset inside the PHY */