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/* * Copyright (C) 2016 IBM Corp. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; either version 2 of the License, or * (at your option) any later version. *//* * The ASPEED SoCs provide typically more than 200 pins for GPIO and other * functions. The SoC function enabled on a pin is determined on a priority * basis where a given pin can provide a number of different signal types. * * The signal active on a pin is described by both a priority level and * compound logical expressions involving multiple operators, registers and * bits. Some difficulty arises as the pin's function bit masks for each * priority level are frequently not the same (i.e. cannot just flip a bit to * change from a high to low priority signal), or even in the same register. * Further, not all signals can be unmuxed, as some expressions depend on * values in the hardware strapping register (which is treated as read-only). * * SoC Multi-function Pin Expression Examples * ------------------------------------------ * * Here are some sample mux configurations from the AST2400 and AST2500 * datasheets to illustrate the corner cases, roughly in order of least to most * corner. The signal priorities are in decending order from P0 (highest). * * D6 is a pin with a single function (beside GPIO); a high priority signal * that participates in one function: * * Ball | Default | P0 Signal | P0 Expression | P1 Signal | P1 Expression | Other * -----+---------+-----------+-----------------------------+-----------+---------------+---------- * D6 GPIOA0 MAC1LINK SCU80[0]=1 GPIOA0 * -----+---------+-----------+-----------------------------+-----------+---------------+---------- * * C5 is a multi-signal pin (high and low priority signals). Here we touch * different registers for the different functions that enable each signal: * * -----+---------+-----------+-----------------------------+-----------+---------------+---------- * C5 GPIOA4 SCL9 SCU90[22]=1 TIMER5 SCU80[4]=1 GPIOA4 * -----+---------+-----------+-----------------------------+-----------+---------------+---------- * * E19 is a single-signal pin with two functions that influence the active * signal. In this case both bits have the same meaning - enable a dedicated * LPC reset pin. However it's not always the case that the bits in the * OR-relationship have the same meaning. * * -----+---------+-----------+-----------------------------+-----------+---------------+---------- * E19 GPIOB4 LPCRST# SCU80[12]=1 | Strap[14]=1 GPIOB4 * -----+---------+-----------+-----------------------------+-----------+---------------+---------- * * For example, pin B19 has a low-priority signal that's enabled by two * distinct SoC functions: A specific SIOPBI bit in register SCUA4, and an ACPI * bit in the STRAP register. The ACPI bit configures signals on pins in * addition to B19. Both of the low priority functions as well as the high * priority function must be disabled for GPIOF1 to be used. * * Ball | Default | P0 Signal | P0 Expression | P1 Signal | P1 Expression | Other * -----+---------+-----------+-----------------------------------------+-----------+----------------------------------------+---------- * B19 GPIOF1 NDCD4 SCU80[25]=1 SIOPBI# SCUA4[12]=1 | Strap[19]=0 GPIOF1 * -----+---------+-----------+-----------------------------------------+-----------+----------------------------------------+---------- * * For pin E18, the SoC ANDs the expected state of three bits to determine the * pin's active signal: * * * SCU3C[3]: Enable external SOC reset function * * SCU80[15]: Enable SPICS1# or EXTRST# function pin * * SCU90[31]: Select SPI interface CS# output * * -----+---------+-----------+-----------------------------------------+-----------+----------------------------------------+---------- * E18 GPIOB7 EXTRST# SCU3C[3]=1 & SCU80[15]=1 & SCU90[31]=0 SPICS1# SCU3C[3]=1 & SCU80[15]=1 & SCU90[31]=1 GPIOB7 * -----+---------+-----------+-----------------------------------------+-----------+----------------------------------------+---------- * * (Bits SCU3C[3] and SCU80[15] appear to only be used in the expressions for * selecting the signals on pin E18) * * Pin T5 is a multi-signal pin with a more complex configuration: * * Ball | Default | P0 Signal | P0 Expression | P1 Signal | P1 Expression | Other * -----+---------+-----------+------------------------------+-----------+---------------+---------- * T5 GPIOL1 VPIDE SCU90[5:4]!=0 & SCU84[17]=1 NDCD1 SCU84[17]=1 GPIOL1