linux-imx

// SPDX-License-Identifier: GPL-2.0

/*

 * Intel Cannon Lake PCH pinctrl/GPIO driver

 *

 * Copyright (C) 2017, Intel Corporation

 * Authors: Andy Shevchenko <andriy.shevchenko@linux.intel.com>

 *          Mika Westerberg <mika.westerberg@linux.intel.com>

 */

​

#include <linux/mod_devicetable.h>

#include <linux/module.h>

#include <linux/platform_device.h>

​

#include <linux/pinctrl/pinctrl.h>

​

#include "pinctrl-intel.h"

​

#define CNL_PAD_OWN     0x020

#define CNL_PADCFGLOCK      0x080

#define CNL_LP_HOSTSW_OWN   0x0b0

#define CNL_H_HOSTSW_OWN    0x0c0

#define CNL_GPI_IE      0x120

​

#define CNL_GPP(r, s, e, g)             \

    {                       \

        .reg_num = (r),             \

        .base = (s),                \

        .size = ((e) - (s) + 1),        \

        .gpio_base = (g),           \

    }

​

#define CNL_NO_GPIO -1

​

#define CNL_COMMUNITY(b, s, e, o, g)            \

    {                       \

        .barno = (b),               \

        .padown_offset = CNL_PAD_OWN,       \

        .padcfglock_offset = CNL_PADCFGLOCK,    \

        .hostown_offset = (o),          \

        .ie_offset = CNL_GPI_IE,        \

        .pin_base = (s),            \

        .npins = ((e) - (s) + 1),       \

        .gpps = (g),                \

        .ngpps = ARRAY_SIZE(g),         \

    }

​

#define CNLLP_COMMUNITY(b, s, e, g)         \

    CNL_COMMUNITY(b, s, e, CNL_LP_HOSTSW_OWN, g)

​

#define CNLH_COMMUNITY(b, s, e, g)          \

    CNL_COMMUNITY(b, s, e, CNL_H_HOSTSW_OWN, g)

​

/* Cannon Lake-H */

static const struct pinctrl_pin_desc cnlh_pins[] = {

    /* GPP_A */

    PINCTRL_PIN(0, "RCINB"),

    PINCTRL_PIN(1, "LAD_0"),

    PINCTRL_PIN(2, "LAD_1"),

    PINCTRL_PIN(3, "LAD_2"),

    PINCTRL_PIN(4, "LAD_3"),

    PINCTRL_PIN(5, "LFRAMEB"),

    PINCTRL_PIN(6, "SERIRQ"),

    PINCTRL_PIN(7, "PIRQAB"),

    PINCTRL_PIN(8, "CLKRUNB"),

    PINCTRL_PIN(9, "CLKOUT_LPC_0"),

    PINCTRL_PIN(10, "CLKOUT_LPC_1"),

    PINCTRL_PIN(11, "PMEB"),

    PINCTRL_PIN(12, "BM_BUSYB"),

    PINCTRL_PIN(13, "SUSWARNB_SUSPWRDNACK"),

    PINCTRL_PIN(14, "SUS_STATB"),

    PINCTRL_PIN(15, "SUSACKB"),

    PINCTRL_PIN(16, "CLKOUT_48"),

    PINCTRL_PIN(17, "SD_VDD1_PWR_EN_B"),

    PINCTRL_PIN(18, "ISH_GP_0"),

    PINCTRL_PIN(19, "ISH_GP_1"),

    PINCTRL_PIN(20, "ISH_GP_2"),

    PINCTRL_PIN(21, "ISH_GP_3"),

    PINCTRL_PIN(22, "ISH_GP_4"),

    PINCTRL_PIN(23, "ISH_GP_5"),

    PINCTRL_PIN(24, "ESPI_CLK_LOOPBK"),

    /* GPP_B */

    PINCTRL_PIN(25, "GSPI0_CS1B"),

    PINCTRL_PIN(26, "GSPI1_CS1B"),

    PINCTRL_PIN(27, "VRALERTB"),

    PINCTRL_PIN(28, "CPU_GP_2"),

    PINCTRL_PIN(29, "CPU_GP_3"),

    PINCTRL_PIN(30, "SRCCLKREQB_0"),

    PINCTRL_PIN(31, "SRCCLKREQB_1"),

    PINCTRL_PIN(32, "SRCCLKREQB_2"),

    PINCTRL_PIN(33, "SRCCLKREQB_3"),

    PINCTRL_PIN(34, "SRCCLKREQB_4"),

    PINCTRL_PIN(35, "SRCCLKREQB_5"),