linux-imx

/*

 * at91 pinctrl driver based on at91 pinmux core

 *

 * Copyright (C) 2011-2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>

 *

 * Under GPLv2 only

 */

​

#include <linux/clk.h>

#include <linux/err.h>

#include <linux/init.h>

#include <linux/of.h>

#include <linux/of_device.h>

#include <linux/of_address.h>

#include <linux/of_irq.h>

#include <linux/slab.h>

#include <linux/interrupt.h>

#include <linux/io.h>

#include <linux/gpio/driver.h>

#include <linux/pinctrl/machine.h>

#include <linux/pinctrl/pinconf.h>

#include <linux/pinctrl/pinctrl.h>

#include <linux/pinctrl/pinmux.h>

/* Since we request GPIOs from ourself */

#include <linux/pinctrl/consumer.h>

​

#include "pinctrl-at91.h"

#include "core.h"

​

#define MAX_GPIO_BANKS      5

#define MAX_NB_GPIO_PER_BANK    32

​

struct at91_pinctrl_mux_ops;

​

struct at91_gpio_chip {

    struct gpio_chip    chip;

    struct pinctrl_gpio_range range;

    struct at91_gpio_chip   *next;      /* Bank sharing same clock */

    int         pioc_hwirq; /* PIO bank interrupt identifier on AIC */

    int         pioc_virq;  /* PIO bank Linux virtual interrupt */

    int         pioc_idx;   /* PIO bank index */

    void __iomem        *regbase;   /* PIO bank virtual address */

    struct clk      *clock;     /* associated clock */

    struct at91_pinctrl_mux_ops *ops;   /* ops */

};

​

static struct at91_gpio_chip *gpio_chips[MAX_GPIO_BANKS];

​

static int gpio_banks;

​

#define PULL_UP     (1 << 0)

#define MULTI_DRIVE (1 << 1)

#define DEGLITCH    (1 << 2)

#define PULL_DOWN   (1 << 3)

#define DIS_SCHMIT  (1 << 4)

#define DRIVE_STRENGTH_SHIFT    5

#define DRIVE_STRENGTH_MASK     0x3

#define DRIVE_STRENGTH   (DRIVE_STRENGTH_MASK << DRIVE_STRENGTH_SHIFT)

#define OUTPUT      (1 << 7)

#define OUTPUT_VAL_SHIFT    8

#define OUTPUT_VAL  (0x1 << OUTPUT_VAL_SHIFT)

#define SLEWRATE_SHIFT  9

#define SLEWRATE_MASK   0x1

#define SLEWRATE    (SLEWRATE_MASK << SLEWRATE_SHIFT)

#define DEBOUNCE    (1 << 16)

#define DEBOUNCE_VAL_SHIFT  17

#define DEBOUNCE_VAL    (0x3fff << DEBOUNCE_VAL_SHIFT)

​

/**

 * These defines will translated the dt binding settings to our internal

 * settings. They are not necessarily the same value as the register setting.

 * The actual drive strength current of low, medium and high must be looked up

 * from the corresponding device datasheet. This value is different for pins

 * that are even in the same banks. It is also dependent on VCC.

 * DRIVE_STRENGTH_DEFAULT is just a placeholder to avoid changing the drive

 * strength when there is no dt config for it.

 */

enum drive_strength_bit {

    DRIVE_STRENGTH_BIT_DEF,

    DRIVE_STRENGTH_BIT_LOW,

    DRIVE_STRENGTH_BIT_MED,

    DRIVE_STRENGTH_BIT_HI,

};

​

#define DRIVE_STRENGTH_BIT_MSK(name)    (DRIVE_STRENGTH_BIT_##name << \

                     DRIVE_STRENGTH_SHIFT)

​

enum slewrate_bit {

    SLEWRATE_BIT_DIS,

    SLEWRATE_BIT_ENA,

};

​