linux-imx

// SPDX-License-Identifier: GPL-2.0

/*

 * Driver for the Intel PMC IPC mechanism

 *

 * (C) Copyright 2014-2015 Intel Corporation

 *

 * This driver is based on Intel SCU IPC driver(intel_scu_ipc.c) by

 *     Sreedhara DS <sreedhara.ds@intel.com>

 *

 * PMC running in ARC processor communicates with other entity running in IA

 * core through IPC mechanism which in turn messaging between IA core ad PMC.

 */

​

#include <linux/acpi.h>

#include <linux/atomic.h>

#include <linux/bitops.h>

#include <linux/delay.h>

#include <linux/device.h>

#include <linux/errno.h>

#include <linux/interrupt.h>

#include <linux/io-64-nonatomic-lo-hi.h>

#include <linux/kernel.h>

#include <linux/module.h>

#include <linux/notifier.h>

#include <linux/pci.h>

#include <linux/platform_device.h>

#include <linux/pm.h>

#include <linux/pm_qos.h>

#include <linux/sched.h>

#include <linux/spinlock.h>

#include <linux/suspend.h>

​

#include <asm/intel_pmc_ipc.h>

​

#include <linux/platform_data/itco_wdt.h>

​

/*

 * IPC registers

 * The IA write to IPC_CMD command register triggers an interrupt to the ARC,

 * The ARC handles the interrupt and services it, writing optional data to

 * the IPC1 registers, updates the IPC_STS response register with the status.

 */

#define IPC_CMD         0x00

#define     IPC_CMD_MSI     BIT(8)

#define     IPC_CMD_SIZE        16

#define     IPC_CMD_SUBCMD      12

#define IPC_STATUS      0x04

#define     IPC_STATUS_IRQ      BIT(2)

#define     IPC_STATUS_ERR      BIT(1)

#define     IPC_STATUS_BUSY     BIT(0)

#define IPC_SPTR        0x08

#define IPC_DPTR        0x0C

#define IPC_WRITE_BUFFER    0x80

#define IPC_READ_BUFFER     0x90

​

/* Residency with clock rate at 19.2MHz to usecs */

#define S0IX_RESIDENCY_IN_USECS(d, s)       \

({                      \

    u64 result = 10ull * ((d) + (s));   \

    do_div(result, 192);            \

    result;                 \

})

​