linux-imx

// SPDX-License-Identifier: GPL-2.0

/*

 * Driver for the Intel SCU IPC mechanism

 *

 * (C) Copyright 2008-2010,2015 Intel Corporation

 * Author: Sreedhara DS (sreedhara.ds@intel.com)

 *

 * SCU running in ARC processor communicates with other entity running in IA

 * core through IPC mechanism which in turn messaging between IA core ad SCU.

 * SCU has two IPC mechanism IPC-1 and IPC-2. IPC-1 is used between IA32 and

 * SCU where IPC-2 is used between P-Unit and SCU. This driver delas with

 * IPC-1 Driver provides an API for power control unit registers (e.g. MSIC)

 * along with other APIs.

 */

​

#include <linux/delay.h>

#include <linux/device.h>

#include <linux/errno.h>

#include <linux/init.h>

#include <linux/interrupt.h>

#include <linux/pci.h>

#include <linux/pm.h>

#include <linux/sfi.h>

​

#include <asm/intel-mid.h>

#include <asm/intel_scu_ipc.h>

​

/* IPC defines the following message types */

#define IPCMSG_WATCHDOG_TIMER 0xF8 /* Set Kernel Watchdog Threshold */

#define IPCMSG_BATTERY        0xEF /* Coulomb Counter Accumulator */

#define IPCMSG_FW_UPDATE      0xFE /* Firmware update */

#define IPCMSG_PCNTRL         0xFF /* Power controller unit read/write */

#define IPCMSG_FW_REVISION    0xF4 /* Get firmware revision */

​

/* Command id associated with message IPCMSG_PCNTRL */

#define IPC_CMD_PCNTRL_W      0 /* Register write */

#define IPC_CMD_PCNTRL_R      1 /* Register read */

#define IPC_CMD_PCNTRL_M      2 /* Register read-modify-write */

​

/*

 * IPC register summary

 *

 * IPC register blocks are memory mapped at fixed address of PCI BAR 0.

 * To read or write information to the SCU, driver writes to IPC-1 memory

 * mapped registers. The following is the IPC mechanism

 *

 * 1. IA core cDMI interface claims this transaction and converts it to a

 *    Transaction Layer Packet (TLP) message which is sent across the cDMI.

 *

 * 2. South Complex cDMI block receives this message and writes it to

 *    the IPC-1 register block, causing an interrupt to the SCU

 *

 * 3. SCU firmware decodes this interrupt and IPC message and the appropriate

 *    message handler is called within firmware.

 */

​

#define IPC_WWBUF_SIZE    20        /* IPC Write buffer Size */

#define IPC_RWBUF_SIZE    20        /* IPC Read buffer Size */

#define IPC_IOC           0x100     /* IPC command register IOC bit */

​

#define PCI_DEVICE_ID_LINCROFT      0x082a

#define PCI_DEVICE_ID_PENWELL       0x080e

#define PCI_DEVICE_ID_CLOVERVIEW    0x08ea

#define PCI_DEVICE_ID_TANGIER       0x11a0

​

/* intel scu ipc driver data */

struct intel_scu_ipc_pdata_t {

    u32 i2c_base;

    u32 i2c_len;

    u8 irq_mode;

};

​

static const struct intel_scu_ipc_pdata_t intel_scu_ipc_lincroft_pdata = {

    .i2c_base = 0xff12b000,

    .i2c_len = 0x10,

    .irq_mode = 0,

};

​

/* Penwell and Cloverview */

static const struct intel_scu_ipc_pdata_t intel_scu_ipc_penwell_pdata = {

    .i2c_base = 0xff12b000,

    .i2c_len = 0x10,

    .irq_mode = 1,

};

​

static const struct intel_scu_ipc_pdata_t intel_scu_ipc_tangier_pdata = {

    .i2c_base  = 0xff00d000,

    .i2c_len = 0x10,

    .irq_mode = 0,

};

​

struct intel_scu_ipc_dev {