linux-imx

/*

 * Copyright (C) 2014 Broadcom Corporation

 *

 * This program is free software; you can redistribute it and/or

 * modify it under the terms of the GNU General Public License as

 * published by the Free Software Foundation version 2.

 *

 * This program is distributed "as is" WITHOUT ANY WARRANTY of any

 * kind, whether express or implied; without even the implied warranty

 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the

 * GNU General Public License for more details.

 */

​

#include <linux/clk.h>

#include <linux/delay.h>

#include <linux/err.h>

#include <linux/io.h>

#include <linux/ioport.h>

#include <linux/math64.h>

#include <linux/module.h>

#include <linux/of.h>

#include <linux/platform_device.h>

#include <linux/pwm.h>

#include <linux/slab.h>

#include <linux/types.h>

​

/*

 * The Kona PWM has some unusual characteristics.  Here are the main points.

 *

 * 1) There is no disable bit and the hardware docs advise programming a zero

 *    duty to achieve output equivalent to that of a normal disable operation.

 *

 * 2) Changes to prescale, duty, period, and polarity do not take effect until

 *    a subsequent rising edge of the trigger bit.

 *

 * 3) If the smooth bit and trigger bit are both low, the output is a constant

 *    high signal.  Otherwise, the earlier waveform continues to be output.

 *

 * 4) If the smooth bit is set on the rising edge of the trigger bit, output

 *    will transition to the new settings on a period boundary (which could be

 *    seconds away).  If the smooth bit is clear, new settings will be applied

 *    as soon as possible (the hardware always has a 400ns delay).

 *

 * 5) When the external clock that feeds the PWM is disabled, output is pegged

 *    high or low depending on its state at that exact instant.

 */

​

#define PWM_CONTROL_OFFSET          0x00000000

#define PWM_CONTROL_SMOOTH_SHIFT(chan)      (24 + (chan))

#define PWM_CONTROL_TYPE_SHIFT(chan)        (16 + (chan))

#define PWM_CONTROL_POLARITY_SHIFT(chan)    (8 + (chan))

#define PWM_CONTROL_TRIGGER_SHIFT(chan)     (chan)

​

#define PRESCALE_OFFSET             0x00000004

#define PRESCALE_SHIFT(chan)            ((chan) << 2)

#define PRESCALE_MASK(chan)         (0x7 << PRESCALE_SHIFT(chan))

#define PRESCALE_MIN                0x00000000

#define PRESCALE_MAX                0x00000007

​

#define PERIOD_COUNT_OFFSET(chan)       (0x00000008 + ((chan) << 3))

#define PERIOD_COUNT_MIN            0x00000002

#define PERIOD_COUNT_MAX            0x00ffffff

​

#define DUTY_CYCLE_HIGH_OFFSET(chan)        (0x0000000c + ((chan) << 3))

#define DUTY_CYCLE_HIGH_MIN         0x00000000

#define DUTY_CYCLE_HIGH_MAX         0x00ffffff

​

struct kona_pwmc {

    struct pwm_chip chip;

    void __iomem *base;

    struct clk *clk;

};

​

static inline struct kona_pwmc *to_kona_pwmc(struct pwm_chip *_chip)

{

    return container_of(_chip, struct kona_pwmc, chip);

}

​

/*

 * Clear trigger bit but set smooth bit to maintain old output.

 */

static void kona_pwmc_prepare_for_settings(struct kona_pwmc *kp,

    unsigned int chan)

{

    unsigned int value = readl(kp->base + PWM_CONTROL_OFFSET);

​

    value |= 1 << PWM_CONTROL_SMOOTH_SHIFT(chan);

    value &= ~(1 << PWM_CONTROL_TRIGGER_SHIFT(chan));

    writel(value, kp->base + PWM_CONTROL_OFFSET);

​

    /*

     * There must be a min 400ns delay between clearing trigger and setting