linux-imx

/*

 * Intel Low Power Subsystem PWM controller driver

 *

 * Copyright (C) 2014, Intel Corporation

 * Author: Mika Westerberg <mika.westerberg@linux.intel.com>

 * Author: Chew Kean Ho <kean.ho.chew@intel.com>

 * Author: Chang Rebecca Swee Fun <rebecca.swee.fun.chang@intel.com>

 * Author: Chew Chiau Ee <chiau.ee.chew@intel.com>

 * Author: Alan Cox <alan@linux.intel.com>

 *

 * This program is free software; you can redistribute it and/or modify

 * it under the terms of the GNU General Public License version 2 as

 * published by the Free Software Foundation.

 */

​

#include <linux/delay.h>

#include <linux/io.h>

#include <linux/iopoll.h>

#include <linux/kernel.h>

#include <linux/module.h>

#include <linux/pm_runtime.h>

#include <linux/time.h>

​

#include "pwm-lpss.h"

​

#define PWM             0x00000000

#define PWM_ENABLE          BIT(31)

#define PWM_SW_UPDATE           BIT(30)

#define PWM_BASE_UNIT_SHIFT     8

#define PWM_ON_TIME_DIV_MASK        0x000000ff

​

/* Size of each PWM register space if multiple */

#define PWM_SIZE            0x400

​

static inline struct pwm_lpss_chip *to_lpwm(struct pwm_chip *chip)

{

    return container_of(chip, struct pwm_lpss_chip, chip);

}

​

static inline u32 pwm_lpss_read(const struct pwm_device *pwm)

{

    struct pwm_lpss_chip *lpwm = to_lpwm(pwm->chip);

​

    return readl(lpwm->regs + pwm->hwpwm * PWM_SIZE + PWM);

}

​

static inline void pwm_lpss_write(const struct pwm_device *pwm, u32 value)

{

    struct pwm_lpss_chip *lpwm = to_lpwm(pwm->chip);

​

    writel(value, lpwm->regs + pwm->hwpwm * PWM_SIZE + PWM);

}

​

static int pwm_lpss_wait_for_update(struct pwm_device *pwm)

{

    struct pwm_lpss_chip *lpwm = to_lpwm(pwm->chip);

    const void __iomem *addr = lpwm->regs + pwm->hwpwm * PWM_SIZE + PWM;

    const unsigned int ms = 500 * USEC_PER_MSEC;

    u32 val;

    int err;

​

    /*

     * PWM Configuration register has SW_UPDATE bit that is set when a new

     * configuration is written to the register. The bit is automatically

     * cleared at the start of the next output cycle by the IP block.

     *

     * If one writes a new configuration to the register while it still has

     * the bit enabled, PWM may freeze. That is, while one can still write

     * to the register, it won't have an effect. Thus, we try to sleep long

     * enough that the bit gets cleared and make sure the bit is not

     * enabled while we update the configuration.

     */

    err = readl_poll_timeout(addr, val, !(val & PWM_SW_UPDATE), 40, ms);

    if (err)

        dev_err(pwm->chip->dev, "PWM_SW_UPDATE was not cleared\n");

​

    return err;

}

​

static inline int pwm_lpss_is_updating(struct pwm_device *pwm)

{

    return (pwm_lpss_read(pwm) & PWM_SW_UPDATE) ? -EBUSY : 0;

}

​

static void pwm_lpss_prepare(struct pwm_lpss_chip *lpwm, struct pwm_device *pwm,

                 int duty_ns, int period_ns)

{

    unsigned long long on_time_div;

    unsigned long c = lpwm->info->clk_rate, base_unit_range;

    unsigned long long base_unit, freq = NSEC_PER_SEC;

    u32 orig_ctrl, ctrl;

​