linux-imx

// SPDX-License-Identifier: GPL-2.0

/*

 * R-Mobile TPU PWM driver

 *

 * Copyright (C) 2012 Renesas Solutions Corp.

 */

​

#include <linux/clk.h>

#include <linux/err.h>

#include <linux/io.h>

#include <linux/init.h>

#include <linux/ioport.h>

#include <linux/module.h>

#include <linux/mutex.h>

#include <linux/of.h>

#include <linux/platform_device.h>

#include <linux/pm_runtime.h>

#include <linux/pwm.h>

#include <linux/slab.h>

#include <linux/spinlock.h>

​

#define TPU_CHANNEL_MAX     4

​

#define TPU_TSTR        0x00    /* Timer start register (shared) */

​

#define TPU_TCRn        0x00    /* Timer control register */

#define TPU_TCR_CCLR_NONE   (0 << 5)

#define TPU_TCR_CCLR_TGRA   (1 << 5)

#define TPU_TCR_CCLR_TGRB   (2 << 5)

#define TPU_TCR_CCLR_TGRC   (5 << 5)

#define TPU_TCR_CCLR_TGRD   (6 << 5)

#define TPU_TCR_CKEG_RISING (0 << 3)

#define TPU_TCR_CKEG_FALLING    (1 << 3)

#define TPU_TCR_CKEG_BOTH   (2 << 3)

#define TPU_TMDRn       0x04    /* Timer mode register */

#define TPU_TMDR_BFWT       (1 << 6)

#define TPU_TMDR_BFB        (1 << 5)

#define TPU_TMDR_BFA        (1 << 4)

#define TPU_TMDR_MD_NORMAL  (0 << 0)

#define TPU_TMDR_MD_PWM     (2 << 0)

#define TPU_TIORn       0x08    /* Timer I/O control register */

#define TPU_TIOR_IOA_0      (0 << 0)

#define TPU_TIOR_IOA_0_CLR  (1 << 0)

#define TPU_TIOR_IOA_0_SET  (2 << 0)

#define TPU_TIOR_IOA_0_TOGGLE   (3 << 0)

#define TPU_TIOR_IOA_1      (4 << 0)

#define TPU_TIOR_IOA_1_CLR  (5 << 0)

#define TPU_TIOR_IOA_1_SET  (6 << 0)

#define TPU_TIOR_IOA_1_TOGGLE   (7 << 0)

#define TPU_TIERn       0x0c    /* Timer interrupt enable register */

#define TPU_TSRn        0x10    /* Timer status register */

#define TPU_TCNTn       0x14    /* Timer counter */

#define TPU_TGRAn       0x18    /* Timer general register A */

#define TPU_TGRBn       0x1c    /* Timer general register B */

#define TPU_TGRCn       0x20    /* Timer general register C */

#define TPU_TGRDn       0x24    /* Timer general register D */

​

#define TPU_CHANNEL_OFFSET  0x10

#define TPU_CHANNEL_SIZE    0x40

​

enum tpu_pin_state {

    TPU_PIN_INACTIVE,       /* Pin is driven inactive */

    TPU_PIN_PWM,            /* Pin is driven by PWM */

    TPU_PIN_ACTIVE,         /* Pin is driven active */

};

​

struct tpu_device;

​

struct tpu_pwm_device {

    bool timer_on;          /* Whether the timer is running */

​

    struct tpu_device *tpu;

    unsigned int channel;       /* Channel number in the TPU */

​

    enum pwm_polarity polarity;

    unsigned int prescaler;

    u16 period;

    u16 duty;

};

​

struct tpu_device {

    struct platform_device *pdev;

    struct pwm_chip chip;

    spinlock_t lock;

​

    void __iomem *base;

    struct clk *clk;

};

​

#define to_tpu_device(c)    container_of(c, struct tpu_device, chip)

​

static void tpu_pwm_write(struct tpu_pwm_device *pwm, int reg_nr, u16 value)