linux-imx

// SPDX-License-Identifier: GPL-2.0

/*

 * Copyright (C) STMicroelectronics 2016

 *

 * Author: Gerald Baeza <gerald.baeza@st.com>

 *

 * Inspired by timer-stm32.c from Maxime Coquelin

 *             pwm-atmel.c from Bo Shen

 */

​

#include <linux/bitfield.h>

#include <linux/mfd/stm32-timers.h>

#include <linux/module.h>

#include <linux/of.h>

#include <linux/platform_device.h>

#include <linux/pwm.h>

​

#define CCMR_CHANNEL_SHIFT 8

#define CCMR_CHANNEL_MASK  0xFF

#define MAX_BREAKINPUT 2

​

struct stm32_pwm {

    struct pwm_chip chip;

    struct mutex lock; /* protect pwm config/enable */

    struct clk *clk;

    struct regmap *regmap;

    u32 max_arr;

    bool have_complementary_output;

    u32 capture[4] ____cacheline_aligned; /* DMA'able buffer */

};

​

struct stm32_breakinput {

    u32 index;

    u32 level;

    u32 filter;

};

​

static inline struct stm32_pwm *to_stm32_pwm_dev(struct pwm_chip *chip)

{

    return container_of(chip, struct stm32_pwm, chip);

}

​

static u32 active_channels(struct stm32_pwm *dev)

{

    u32 ccer;

​

    regmap_read(dev->regmap, TIM_CCER, &ccer);

​

    return ccer & TIM_CCER_CCXE;

}

​

static int write_ccrx(struct stm32_pwm *dev, int ch, u32 value)

{

    switch (ch) {

    case 0:

        return regmap_write(dev->regmap, TIM_CCR1, value);

    case 1:

        return regmap_write(dev->regmap, TIM_CCR2, value);

    case 2:

        return regmap_write(dev->regmap, TIM_CCR3, value);

    case 3:

        return regmap_write(dev->regmap, TIM_CCR4, value);

    }

    return -EINVAL;

}

​

#define TIM_CCER_CC12P (TIM_CCER_CC1P | TIM_CCER_CC2P)

#define TIM_CCER_CC12E (TIM_CCER_CC1E | TIM_CCER_CC2E)

#define TIM_CCER_CC34P (TIM_CCER_CC3P | TIM_CCER_CC4P)

#define TIM_CCER_CC34E (TIM_CCER_CC3E | TIM_CCER_CC4E)

​

/*

 * Capture using PWM input mode:

 *                              ___          ___

 * TI[1, 2, 3 or 4]: ........._|   |________|

 *                             ^0  ^1       ^2

 *                              .   .        .

 *                              .   .        XXXXX

 *                              .   .   XXXXX     |

 *                              .  XXXXX     .    |

 *                            XXXXX .        .    |

 * COUNTER:        ______XXXXX  .   .        .    |_XXX

 *                 start^       .   .        .        ^stop

 *                      .       .   .        .

 *                      v       v   .        v

 *                                  v

 * CCR1/CCR3:       tx..........t0...........t2

 * CCR2/CCR4:       tx..............t1.........

 *

 * DMA burst transfer:          |            |

 *                              v            v

 * DMA buffer:                  { t0, tx }   { t2, t1 }