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committed c07bbfe7026x
dev_err(&pdev->dev, "Failed to read a valid default voltage selector.\n");// SPDX-License-Identifier: GPL-2.0+//// Copyright (C) 2011 Freescale Semiconductor, Inc. All Rights Reserved./* 64 cycles per step *//* cycle based on 24M OSC */struct anatop_regulator { u32 control_reg; struct regmap *anatop; int vol_bit_shift; int vol_bit_width; u32 delay_reg; int delay_bit_shift; int delay_bit_width; int min_bit_val; int min_voltage; int max_voltage; struct regulator_desc rdesc; struct regulator_init_data *initdata; bool bypass; int sel;};static int anatop_regmap_set_voltage_time_sel(struct regulator_dev *reg, unsigned int old_sel, unsigned int new_sel){ struct anatop_regulator *anatop_reg = rdev_get_drvdata(reg); u32 val; int ret = 0; /* check whether need to care about LDO ramp up speed */ if (anatop_reg->delay_bit_width && new_sel > old_sel) { /* * the delay for LDO ramp up time is * based on the register setting, we need * to calculate how many steps LDO need to * ramp up, and how much delay needed. (us) */ regmap_read(anatop_reg->anatop, anatop_reg->delay_reg, &val); val = (val >> anatop_reg->delay_bit_shift) & ((1 << anatop_reg->delay_bit_width) - 1); ret = (new_sel - old_sel) * (LDO_RAMP_UP_UNIT_IN_CYCLES << val) / LDO_RAMP_UP_FREQ_IN_MHZ + 1; } return ret;}static int anatop_regmap_enable(struct regulator_dev *reg){ struct anatop_regulator *anatop_reg = rdev_get_drvdata(reg); int sel; sel = anatop_reg->bypass ? LDO_FET_FULL_ON : anatop_reg->sel; return regulator_set_voltage_sel_regmap(reg, sel);}static int anatop_regmap_disable(struct regulator_dev *reg){ return regulator_set_voltage_sel_regmap(reg, LDO_POWER_GATE);}static int anatop_regmap_is_enabled(struct regulator_dev *reg){ return regulator_get_voltage_sel_regmap(reg) != LDO_POWER_GATE;}static int anatop_regmap_core_set_voltage_sel(struct regulator_dev *reg, unsigned selector){ struct anatop_regulator *anatop_reg = rdev_get_drvdata(reg); int ret;