linux-imx

/*

 * Copyright (c) 2017, Impinj, Inc.

 *

 * i.MX7 System Reset Controller (SRC) driver

 *

 * Author: Andrey Smirnov <andrew.smirnov@gmail.com>

 *

 * This program is free software; you can redistribute it and/or modify

 * it under the terms of the GNU General Public License as published by

 * the Free Software Foundation; version 2 of the License.

 *

 * This program is distributed in the hope that it will be useful,

 * but WITHOUT ANY WARRANTY; without even the implied warranty of

 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the

 * GNU General Public License for more details.

 */

​

#include <linux/mfd/syscon.h>

#include <linux/mod_devicetable.h>

#include <linux/of_device.h>

#include <linux/platform_device.h>

#include <linux/reset-controller.h>

#include <linux/regmap.h>

#include <dt-bindings/reset/imx7-reset.h>

#include <dt-bindings/reset/imx8mq-reset.h>

​

struct imx7_src_signal {

    unsigned int offset, bit;

};

​

struct imx7_src_variant {

    const struct imx7_src_signal *signals;

    unsigned int signals_num;

    struct reset_control_ops ops;

};

​

struct imx7_src {

    struct reset_controller_dev rcdev;

    struct regmap *regmap;

    const struct imx7_src_signal *signals;

};

​

enum imx7_src_registers {

    SRC_A7RCR0      = 0x0004,

    SRC_M4RCR       = 0x000c,

    SRC_ERCR        = 0x0014,

    SRC_HSICPHY_RCR     = 0x001c,

    SRC_USBOPHY1_RCR    = 0x0020,

    SRC_USBOPHY2_RCR    = 0x0024,

    SRC_MIPIPHY_RCR     = 0x0028,

    SRC_PCIEPHY_RCR     = 0x002c,

    SRC_DDRC_RCR        = 0x1000,

};

​

static int imx7_reset_update(struct imx7_src *imx7src,

                 unsigned long id, unsigned int value)

{

    const struct imx7_src_signal *signal = &imx7src->signals[id];

​

    return regmap_update_bits(imx7src->regmap,

                  signal->offset, signal->bit, value);

}

​

static const struct imx7_src_signal imx7_src_signals[IMX7_RESET_NUM] = {

    [IMX7_RESET_A7_CORE_POR_RESET0] = { SRC_A7RCR0, BIT(0) },

    [IMX7_RESET_A7_CORE_POR_RESET1] = { SRC_A7RCR0, BIT(1) },

    [IMX7_RESET_A7_CORE_RESET0]     = { SRC_A7RCR0, BIT(4) },

    [IMX7_RESET_A7_CORE_RESET1] = { SRC_A7RCR0, BIT(5) },

    [IMX7_RESET_A7_DBG_RESET0]  = { SRC_A7RCR0, BIT(8) },

    [IMX7_RESET_A7_DBG_RESET1]  = { SRC_A7RCR0, BIT(9) },

    [IMX7_RESET_A7_ETM_RESET0]  = { SRC_A7RCR0, BIT(12) },

    [IMX7_RESET_A7_ETM_RESET1]  = { SRC_A7RCR0, BIT(13) },

    [IMX7_RESET_A7_SOC_DBG_RESET]   = { SRC_A7RCR0, BIT(20) },

    [IMX7_RESET_A7_L2RESET]     = { SRC_A7RCR0, BIT(21) },

    [IMX7_RESET_SW_M4C_RST]     = { SRC_M4RCR, BIT(1) },

    [IMX7_RESET_SW_M4P_RST]     = { SRC_M4RCR, BIT(2) },

    [IMX7_RESET_EIM_RST]        = { SRC_ERCR, BIT(0) },

    [IMX7_RESET_HSICPHY_PORT_RST]   = { SRC_HSICPHY_RCR, BIT(1) },

    [IMX7_RESET_USBPHY1_POR]    = { SRC_USBOPHY1_RCR, BIT(0) },

    [IMX7_RESET_USBPHY1_PORT_RST]   = { SRC_USBOPHY1_RCR, BIT(1) },

    [IMX7_RESET_USBPHY2_POR]    = { SRC_USBOPHY2_RCR, BIT(0) },

    [IMX7_RESET_USBPHY2_PORT_RST]   = { SRC_USBOPHY2_RCR, BIT(1) },

    [IMX7_RESET_MIPI_PHY_MRST]  = { SRC_MIPIPHY_RCR, BIT(1) },

    [IMX7_RESET_MIPI_PHY_SRST]  = { SRC_MIPIPHY_RCR, BIT(2) },

    [IMX7_RESET_PCIEPHY]        = { SRC_PCIEPHY_RCR, BIT(2) | BIT(1) },

    [IMX7_RESET_PCIEPHY_PERST]  = { SRC_PCIEPHY_RCR, BIT(3) },

    [IMX7_RESET_PCIE_CTRL_APPS_EN]  = { SRC_PCIEPHY_RCR, BIT(6) },

    [IMX7_RESET_PCIE_CTRL_APPS_TURNOFF] = { SRC_PCIEPHY_RCR, BIT(11) },

    [IMX7_RESET_DDRC_PRST]      = { SRC_DDRC_RCR, BIT(0) },

    [IMX7_RESET_DDRC_CORE_RST]  = { SRC_DDRC_RCR, BIT(1) },

};

​