linux-imx

/*

 * Copyright 2008-2009 Freescale Semiconductor, Inc. All Rights Reserved.

 * Copyright 2010 Orex Computed Radiography

 */

​

/*

 * The code contained herein is licensed under the GNU General Public

 * License. You may obtain a copy of the GNU General Public License

 * Version 2 or later at the following locations:

 *

 * http://www.opensource.org/licenses/gpl-license.html

 * http://www.gnu.org/copyleft/gpl.html

 */

​

/* based on rtc-mc13892.c */

​

/*

 * This driver uses the 47-bit 32 kHz counter in the Freescale DryIce block

 * to implement a Linux RTC. Times and alarms are truncated to seconds.

 * Since the RTC framework performs API locking via rtc->ops_lock the

 * only simultaneous accesses we need to deal with is updating DryIce

 * registers while servicing an alarm.

 *

 * Note that reading the DSR (DryIce Status Register) automatically clears

 * the WCF (Write Complete Flag). All DryIce writes are synchronized to the

 * LP (Low Power) domain and set the WCF upon completion. Writes to the

 * DIER (DryIce Interrupt Enable Register) are the only exception. These

 * occur at normal bus speeds and do not set WCF.  Periodic interrupts are

 * not supported by the hardware.

 */

​

#include <linux/io.h>

#include <linux/clk.h>

#include <linux/delay.h>

#include <linux/module.h>

#include <linux/platform_device.h>

#include <linux/rtc.h>

#include <linux/sched.h>

#include <linux/spinlock.h>

#include <linux/workqueue.h>

#include <linux/of.h>

​

/* DryIce Register Definitions */

​

#define DTCMR     0x00           /* Time Counter MSB Reg */

#define DTCLR     0x04           /* Time Counter LSB Reg */

​

#define DCAMR     0x08           /* Clock Alarm MSB Reg */

#define DCALR     0x0c           /* Clock Alarm LSB Reg */

#define DCAMR_UNSET  0xFFFFFFFF  /* doomsday - 1 sec */

​

#define DCR       0x10           /* Control Reg */

#define DCR_TDCHL (1 << 30)      /* Tamper-detect configuration hard lock */

#define DCR_TDCSL (1 << 29)      /* Tamper-detect configuration soft lock */

#define DCR_KSSL  (1 << 27)      /* Key-select soft lock */

#define DCR_MCHL  (1 << 20)      /* Monotonic-counter hard lock */

#define DCR_MCSL  (1 << 19)      /* Monotonic-counter soft lock */

#define DCR_TCHL  (1 << 18)      /* Timer-counter hard lock */

#define DCR_TCSL  (1 << 17)      /* Timer-counter soft lock */

#define DCR_FSHL  (1 << 16)      /* Failure state hard lock */

#define DCR_TCE   (1 << 3)       /* Time Counter Enable */

#define DCR_MCE   (1 << 2)       /* Monotonic Counter Enable */

​