linux-imx

// SPDX-License-Identifier: GPL-2.0

/*

 * SuperH On-Chip RTC Support

 *

 * Copyright (C) 2006 - 2009  Paul Mundt

 * Copyright (C) 2006  Jamie Lenehan

 * Copyright (C) 2008  Angelo Castello

 *

 * Based on the old arch/sh/kernel/cpu/rtc.c by:

 *

 *  Copyright (C) 2000  Philipp Rumpf <prumpf@tux.org>

 *  Copyright (C) 1999  Tetsuya Okada & Niibe Yutaka

 */

#include <linux/module.h>

#include <linux/mod_devicetable.h>

#include <linux/kernel.h>

#include <linux/bcd.h>

#include <linux/rtc.h>

#include <linux/init.h>

#include <linux/platform_device.h>

#include <linux/seq_file.h>

#include <linux/interrupt.h>

#include <linux/spinlock.h>

#include <linux/io.h>

#include <linux/log2.h>

#include <linux/clk.h>

#include <linux/slab.h>

#ifdef CONFIG_SUPERH

#include <asm/rtc.h>

#else

/* Default values for RZ/A RTC */

#define rtc_reg_size        sizeof(u16)

#define RTC_BIT_INVERTED        0   /* no chip bugs */

#define RTC_CAP_4_DIGIT_YEAR    (1 << 0)

#define RTC_DEF_CAPABILITIES    RTC_CAP_4_DIGIT_YEAR

#endif

​

#define DRV_NAME    "sh-rtc"

​

#define RTC_REG(r)  ((r) * rtc_reg_size)

​

#define R64CNT      RTC_REG(0)

​

#define RSECCNT     RTC_REG(1)  /* RTC sec */

#define RMINCNT     RTC_REG(2)  /* RTC min */

#define RHRCNT      RTC_REG(3)  /* RTC hour */

#define RWKCNT      RTC_REG(4)  /* RTC week */

#define RDAYCNT     RTC_REG(5)  /* RTC day */

#define RMONCNT     RTC_REG(6)  /* RTC month */

#define RYRCNT      RTC_REG(7)  /* RTC year */

#define RSECAR      RTC_REG(8)  /* ALARM sec */

#define RMINAR      RTC_REG(9)  /* ALARM min */

#define RHRAR       RTC_REG(10) /* ALARM hour */

#define RWKAR       RTC_REG(11) /* ALARM week */

#define RDAYAR      RTC_REG(12) /* ALARM day */

#define RMONAR      RTC_REG(13) /* ALARM month */

#define RCR1        RTC_REG(14) /* Control */

#define RCR2        RTC_REG(15) /* Control */

​

/*

 * Note on RYRAR and RCR3: Up until this point most of the register

 * definitions are consistent across all of the available parts. However,

 * the placement of the optional RYRAR and RCR3 (the RYRAR control